I'd *really* rather not.
> The low level is 0.8
> against a 1.65 center.
1) That's a marketing number, not real silicon. 0.8 is holy,
passed down from our distant ancestors, and a matter of faith
as much as the flatness of the Earth.
2) Even in the Holy Dogma of 0.8, the center is 1.5 because 0.8
is only defined as the low when the supply is at minimum.
3) OF COURSE you can set the voltage levels to silly values. You
could also set the switch point to Vddq-200mv in a system with
separate supplies. There are an infinite number of ways to
screw things up. The original question, however, was general
and not specific to ECL100K
> Assuming the active level is used less often, you
> gain noise margin for the inactive level.
The implicit assumption is that it's better to have an active signal
read as inactive than an inactive signal read as active. Offhand I
can think of several exceptions.
> Also, drive strength are not
> equal between N and P, usually favoring the pull-down. Another asymmetry to
> consider for timing edges and slew rates. If you are defining your own
> private interface with levels slew rates, then there is little difference.
> But when making signal activity level choices for existing signaling
> protocols, you may want to look at the relative noise margins.
If you're not careful before long you end up with a mess like PCI or
AGP where the problems caused by one assymetry are addressed by a second
assymetry, which in turn causes problems that are addressed by two more,
and so on and so on. (Extra pulldown strength turns into more ground
noise which degrades already-mimimal input low margins etc.)
The fact remains that your effective noise margin is the lower of the
two (0->1 vs 1->0) and the best results occur when the switchpoint is
centered. ANY other situation requires careful and application-specific
analysis to determine where the risks lie. (Active-LOW reset signals
with low input thresholds avoid false resets, but active LOW framing
signals with low thresholds lose packets.)
> -----Original Message-----
> From: D. C. Sessions [mailto:firstname.lastname@example.org]
> Sent: Thursday, April 22, 1999 8:39 AM
> To: email@example.com
> Subject: Re: [SI-LIST] : Signal Polarities
> Kassem Abdallah wrote:
> > Hi All,
> > I wonder if someone can briefly illustrate the pros and cons of using
> > Active low signals versus Active High signals.
> > - Form both views: a chip design and a board level design
> > - From the Drivers technology selection.
> > - From a Connection view:
> > (a) in case of a piont to point connection.
> > (b) multi-node connection.
> Since you need to be able to transition in both directions,
> there is no difference whatsoever.
-- D. C. Sessions firstname.lastname@example.org
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