Re: [SI-LIST] : IBIS simulation of ZBT SRAM
D. C. Sessions (email@example.com)
Mon, 04 Oct 1999 12:29:13 -0700
Arrigo Benedetti wrote:
> Dear SI experts,
> I'd like to know if any of you had better luck in doing signal
> integrity simulations with ZBT SRAMs. I am simulating a
> bidirectional data bus between a ZBT and a Xilinx Virtex device. What
> is strange is that the rise time of the ZBT driver is slow
> compared to the clock period even for model files of devices in the
> 166-200 MHz clock frequency range. I tried IBIS files from Micron, IDT
> and Cypress and the 10-90% rise time is always in the 1.1-2.4 ns. One
> of these models is so slow that at 166 MHz the voltage on the line
> does not even reach VDD.
What are the fixture values in the [Rising Waveform] and
[Falling Waveform] sections? Ludicrously long edge times
are usually a consequence of traditional (don't get me
started) capacitive characterization loads.
If you could post the V/T sections it might be even better.
D. C. Sessions
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****