RE: [SI-LIST] : Decoupling caps and power plane effects

Doug Piper (doug.piper@wovenelectronics.com)
Mon, 17 May 1999 17:24:08 -0400

Gary,
Another raw lead in your territory, but they are talking the right stuff!

Doug Piper
Woven Electronics
P.O. Box 189
Mauldin, SC 29662
PH 864-967-1751
FAX 864-963-1761
e-mail: doug.piper@wovenelectronics.com
www.wovenelectronics.com

-----Original Message-----
From: Ron Miller [SMTP:rmiller@Brocade.COM]
Sent: Monday, May 17, 1999 4:25 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Decoupling caps and power plane effects

> Hi Todd

Within your own company, Intel, a small group is working on test
interfaces.
Arthur Frazier , a microwave engineer works in this group, and has MDS
Microwave Development System(simiulator) from HP which has models for
power/ground in a matrix form. This tool does what you need accurately.

Ron Miller

> To calculate the required number of decoupling capacitance for a given
> motherboard, I am trying to setup lumped RLC circuit to model the
behavior
> of a realistic capacitor discharging into a power plane. The modeling of
> the realistic capacitor just involved RLC elements all in series. The
ESR
> is determined from the vendors datasheet. The ESL from the datasheet as
> well as the loop inductance when placed on the PCB. To model the
presence
> of the power plane is proving more involved.
>
> When a chip on a circuit board has its initial current draw from its
outputs
> switching, the power plane is the first to respond with current. This is
> due to the low inductance of the power plane. Next the ceramic
capacitors
> respond, followed by the higher ESL caps and then finally the power
supply.
> The effect of the power plane responding to the IC's current draw is the
> topic which I would appreciate assistance on. At time t=0, an IC chip's
> outputs switch and its power pins will draw a current Io from the power
> plane of a motherboard. Since the power plane is essentially a large
> capacitor, its discharging current will decrease the voltage level of the
> plane until the ceramics respond to stabilize...then the bulks...then the
> power supply. The rate at which the power plane discharges is of
interest
> to me. If the effective capacitance of the power plane seen by a chip
can
> be gauged, then the discharge rate of the power plane supplying current
to
> some load can be modeled with a lumped capacitave element. With the
> discharge of the power supply predictable, then decoupling capacitance
can
> be calculated to prevent the power plane voltage from drooping below a
> specified voltage.
>
> Has anyone done any power/ground studies that would shed light on this
> problem? Are any of my assumptions invalid?
>
> Thanks all.
>
> Todd Bermensolo
> Intel Corp
> High End Server Division
>
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--
Ronald B. Miller  _\\|//_  Signal Integrity Engineer
(408)487-8017    (' 0-0 ') fax(408)487-8017
     ==========0000-(_)0000===========
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