RE: [SI-LIST] : Chip level Vs Board level SI

Shenoy, Jay (Jay.Shenoy@VLSI.com)
Mon, 26 Apr 1999 13:38:45 -0700

Hi Arun,

Over the weekend I looked through over my collection of references and
think that
the following two are good starting points:
1) A collection of papers edited by Stewart Tewksbury (published by IEEE
and titled
Microelectronic System Interconnects) has on-chip interconnect as one of
it's three
sections. This collection is a little dated though (1991 I think).
2) A tutorial session ( I didnt attend it, just obtained the handouts) in
the latest ICCAD
conference on high speed on chip interconnect.

Your library should probably have the former, not sure if you would be
able to acess
the latter.

I wanted to ask you a favor as well: Could you, in brief, describe the
high speed design
activities at CEDT? This is for my personal curiosity, I am eager to find
out anything and
everything going on in this field in India....

Thanks
Jayarama

> -----Original Message-----
> From: Arun Chandrashekar [SMTP:carun@cedt.iisc.ernet.in]
> Sent: Thursday, April 15, 1999 11:11 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Chip level Vs Board level SI
>
> Hello all,
> I need some information on factors that distinguish signal
> integrity problems at the chip level and at the board level. I
> personally feel that board level SI problems are more prominent as I do
> not have much idea about the chip level SI problems. Also, most articles
> I come across do not seem to address the SI problems at the chip level.
> Can u help me throw light on this point and clarify ?
> Thanks and Regards
> ARUN C
> Research Associate
> CEDT, Indian Institute of Science
> Bangalore, Karnataka, INDIA
> 560012
> Ph: +91-80-3341810
> FAX: +91-80-3341808
> Homepage URL: http://shravana.cedt.iisc.ernet.in/~carun
>
>
>
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