> Sometimes we have just one low inductance supply (usually ground)
My condolences :-)
> and if
> we had enough capacitance on-chip then we can still run high data
> rates with a poor power return for outputs that are CMOS that use
> both pull-up and pull-down such as CMOS full-swing and LVTTL.
Ummmm... Yeah, but that's a LOT of capacitance. Assuming that you're
running 12:1:3 into 50 ohms reflected-wave with ground inductance of
5 nH/pin, you have a per-pin L/R of (12)(5 nH)/(100 ohms) or 600 ps.
To get the RC product into the same ballpark you'd have to have
(600 ps)/(100 ohms) or 6 pF per pin. In practice this would be quite
a bit short of sufficient even with a very favorable 5 nH per pin, but
6 pF/pin is still enough to nearly double the size of your I/O ring.
> in some cases it is a 'limited benefit' but in others it is not.
I suppose if you have a design that's massively core-limited (as in less
than half of the available I/O ring used) then it might make some sense,
but for low-pincount devices with modest I/O needs it's about as cheap
to use a better package -- and at best this stunt will only work to get
I/O performance into the 'modest' range.
> > IMHO the best bet for minimizing SSO transients is to use balanced codes
> > such as 8b/10b so that there isn't any substantial common-mode current.
> > Actually saves pins and cuts jitter too.
> Not sure where you are coming from here. 8b/10b will work if you
> have a DC block in your system. But for SSO transients you've got
> to get current supplied during the switching event - not just average
> out the current demand over 10 bits.
Parallel 8b/10b. Explained in another message.
> Can the confusion be that you have a single rail output driver, such
> as GTL, in mind whereas many of us are thinking more of a two-rail
> output driver such as LVTTL or full-swing CMOS?
Wash your mouth!
Actually, I *have* done some really fast current-mode stuff that had
to be open-drain because we couldn't manage the crossover distortion
across process. I'd rather everyone forgot it, though, and GTL is
one sin I've never committed. Push-pull is *much* more fun. (e.g.,
SSTL, HSTL, GLVDS, etc.)
> > > -----Original Message-----
> > > From: D. C. Sessions [mailto:email@example.com]
> > > Sent: Monday, September 20, 1999 9:08 AM
> > > To: firstname.lastname@example.org
> > > Subject: Re: [SI-LIST] : RE: Another decoupling question
> > >
> > > "Volk, Andrew M" wrote:
> > > >
> > > > Chris -
> > > >
> > > > I agree the best capacitance is on-die. It is expensive in die area, but
> > > > becoming more and more essential as edge rates and speeds increase.
> > > > However, there exist devices already without such provisions and I was
> > > still
> > > > wondering whether capacitors can be placed under BGA packages to help
> > > > existing power decoupling problems. Is it cost effective and
> > > > manufacturable?
> > >
> > > > -----Original Message-----
> > > > From: Chris Cheng [mailto:email@example.com]
> > > > Sent: Friday, September 17, 1999 1:52 PM
> > > > To: firstname.lastname@example.org
> > > > Subject: RE: [SI-LIST] : RE: Another decoupling question
> > > >
> > > > for ~10nf, you are better of putting it insider the die. (yes, on
> > > > die decouping)
> > > > chris
-- D. C. Sessions email@example.com
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