[SI-LIST] : question about timing analysis

Andrew Phillips (andrew@scs.ch)
Thu, 27 May 1999 16:01:43 +0200

Hello,

Have been doing some IBIS simulations of a circuit to determine
interconnection delays and whether they are small enough to satisfy
timing requirements. The datasheet for the device driving the circuit
states that all timing parameters are quoted as if the driver was
connected to a 50ohm series resistor and a 30pF load.

Now, when I simulate the driver connected to this load it shows that
rise and fall waveforms at the load take 2.5ns to reach threshold
voltages.

Instead of having this test load I (of course) actually have my specific
circuit. The voltages at the load now take 5ns to settle.

The driver is an address line going to a SDRAM. The datasheet for the
driver says that the address is valid 6ns after a clock.

Here's the question - to determine whether the address will be settled
in time at the SDRAM input is it safe to assume that I can subtract the
2.5ns (for the test load) from the address valid timing spec and instead
add the settling time of my actual circuit (i.e. address valid after
clock = 6ns - 2.5ns + 5ns = 8.5ns) ??

Thanks for any help,

Andrew Phillips
Supercomputing Systems AG
Zurich, Switzerland

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****