Re[2]: [SI-LIST] : Via Capacitances ...

mcheong@molex.com
Mon, 12 Jul 1999 09:46:02 -0500

I agree with Ron's email on via being nothing but a capacitive stub.

One can verify that by measuring a typical via with a TDR.
Run a length of trace with an open via in the middle and launch a TDR signal
(~35pS) from one end. Make sure the line is terminated in its characteristic
impedance. You will discover a negative reflection (capacitive discontinuity).

The equivalent capacitance can be derived by utilizing the reflected voltage,
risetime, incident voltage and Zo.

Michael Cheong

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Molex Incorporated
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____________________Reply Separator____________________
Subject: Re: [SI-LIST] : Via Capacitances ...
Author: Ron Miller <rmiller@Brocade.COM>
Date: 7/9/99 1:22 PM

Mike

I agree that when the via as not in the signal path it may look capacitive.

The reason it looks capacitive is that it is an open stub. There is a
reflection at the end of the line whenever you have an open stub
and it look capacitive. It should be modeled as an open stub.

Ron miller

Mike Degerstrom wrote:

> Ron makes a good point in that vias are more inductive than capacitive.
> I would suppose that if you had a very weak and/or slow driver one
> could treat the vias as lumped capacitance. Other examples where
> vias could be treated as capacitors is when they are used for test
> points and do not carry any real current. We studied many MCM
> technologies a few years ago and the vias were almost exclusively
> capacitive when hit with a 20ps risetime TDR. Even a MCM-L
> technology had capacitive vias and today's advanced pcb board
> are not that much different from a four year old MCM-L process.
> So I think that one would have to consider the technology and that
> vias within the same technology can different capacitive/inductive
> ratios depending on how many layers the signal tranversed.
>
> Mike
>
> On Jul 9, 9:50am, Ron Miller wrote:
> > Subject: Re: [SI-LIST] : Via Capacitances ...
> > Doug
> >
> > I modeled a via some time back with ground planes and
> > clearance holes through it. I had intended to use the capacitance
> > to make up for an inductance and needed 300 ff.
> >
> > I used an OEA field solver Metal and to my amazement there was
> > hardly any capacitance. I surmised that this was due to the small
> > area of the ground planes in tha horizontal direction. Since I needed
> > capacitance I added some big fat ground vias all around the signal
> > via, and got the 300 ff.
> >
> > Also, HP ADS which is the cadillac of RF simulators models vias
> > as inductor, as does Touchstone before EEsof got swallowed up by
> > HP.
> >
> > Ron
> >
> > Douglas McKean wrote:
> >
> > > Could someone give rough estimate
> > > of via capacitance?
> > >
> > > I'm thinking the orientation of the traces
> > > connected to the via have a major impact.
> > >
> > > For instance, an .062 board with a via
> > > from one side to the other, different
> > > capacitances would be had with the two
> > > following constructions ...
> > >
> > > I. Top Trace
> > > -------------
> > > |via
> > > -------------
> > > Bottom Trace
> > >
> > > II. Top Trace
> > > -------------
> > > |via
> > > -------------
> > > Bottom Trace
> > >
> > > Ideas? Comments?
> > >
> > > Regards, Doug McKean
> > >
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> > --
> > Ronald B. Miller _\\|//_ Signal Integrity Engineer
> > (408)487-8017 (' 0-0 ') fax(408)487-8017
> > ==========0000-(_)0000===========
> > Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131
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> >
> >
> >
> >
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> >-- End of excerpt from Ron Miller
>
> --
> _______________________________________________________________
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