[SI-LIST] : EPEP '99 Final Program

Madhavan Swaminathan (madhavan.swaminathan@ece.gatech.edu)
Thu, 02 Sep 1999 12:55:53 -0700

Please find attached the final program for the 8th Topical Meeting on
Electrical
Performance of Electronic Packaging.

Please find attached the final program for the 8th Topical Meeting on
Electrical
Performance of Electronic Packaging.



Best Regards,
Madhavan Swaminathan
Ravi Kaw
Conference Co-Chairs

IEEE
The Institute of Electrical
and Electronic Engineers, Inc.

Program
------------------------------------
------------------------------------

8th Topical Meeting on
Electrical Performance
of Electronic Packaging



EPEP '98


Sponsors:

The IEEE Microwave
Theory and Techniques Society

and

The IEEE Components, Packaging and
Manufacturing Technology Society


October 25 - 27, 1999
Catamaran Hotel
San Diego, California


logos here

INTRODUCTION

The 8th Topical Meeting on Electrical Performance of Electronic
Packaging
provides a forum for the presentation and discussion of the latest
advances
in electrical design, analysis and characterization of on-chip and
packaging
interconnections and structures for digital, mixed signal, RF, microwave
and
mm-wave applications. The meeting is aimed at bringing together
researchers
and practical engineers from industry, universities and government
laboratories from around the world to address all current and future
issues
affecting the electrical performance of high-speed electronic systems.
The
conference is organized into thirteen oral sessions and one open poster
forum
for one-on-one discussions.

Two important areas are being addressed in the plenary session on
gigascale
integration and microwave multichip modules to set the stage for the
meeting. In addition, seven invited talks address important topics,
such as
on-chip wiring design challenges, on-chip power distribution,
simultaneous
switching noise, on-chip interconnect modeling and microwave package
modeling. Eight short courses are also being offered on the day prior to
the
start of the meeting. The tutorials are given by well known experts in
the
field and cover important topics such as interconnect design,
measurements,
modeling, characterization and power distribution. A tour of the
ceramic
facility is also being arranged by Kyocera America on the second day of
the
meeting.

Two best student paper awards are being offered this year sponsored by
Intel
Corporation and Kyocera. A total of 10 student papers will be competing
for
these awards. The award selection will be made at the meeting by a
committee. Last year the best student paper award sponsored by Intel
Corporation was given to Mr. Pavan K. Gunupudi from Carleton University
for
his paper entitled, 93Efficient Simulation of High-Speed Distributed
Interconnects Using Krylov-Subspace Techniques 94. Informal
interactions are
greatly encouraged during the time available between sessions, the
evening
open forum and the dinner banquet.

The meeting chairs thank the invited speakers, authors, presenters,
tutorial
instructors and technical program committee members for their
contributions
in putting together such an outstanding technical program. The
sponsorship
of the IEEE Microwave Theory and Techniques Society and the IEEE
components,
Packaging and Manufacturing Technology Society is acknowledged and the
individual sponsorships are greatly appreciated.


Madhavan Swaminathan C. Park
Ravi Kaw Regional Chair
Meeting Co-Chairs


Technical Program Committee

T. Arabi, Intel Corporation
A. Cangellaris, University of Illinois
A. Deutsch, IBM Corporation
P. Franzon, North Carolina State University
R. Frye, Lucent Technologies
T. Itoh, UCLA
R. Jackson, University of Massachusetts
G. Katopis, IBM Corporation
R. Kaw, Hewlett-Packard
R. Kemerly, US Air Force
K. Lee, Hewlett-Packard
L. Martens, University of Gent
C. Park, Kyocera America, Inc.
J. Prince, University of Arizona
M. Swaminathan, Georgia Institute of Technology
V. Tripathi, Oregon State University
D. Williams, NIST

International Advisory Committee

D. DeZutter, University of Gent
W. Menzel, Ulm University
R. Mittra, Pennsylvania State University
O. Palusinski, University of Arizona
T. Sarkar, Syracuse University
R. Sturdivant, Raytheon Corporation
R. Tummala, Georgia Institute of Technology




General Information

Registration

For Short Courses - Sunday, October 24, 1999

Registration will be held in the Aviary Foyer of the Catamaran Resort
Hotel,
beginning at 7:30 a.m. Registration fee for each Short Course is
$250.00.
Registration fee includes course material and a refreshment break.

For The Meeting - October 25 - 27, 1999

Registration will be held in the Aviary Foyer of The Catamaran Resort
Hotel,
on Sunday, October 24, 1999 from 9:00 am to 5:00 p.m. and resumes on
Monday,
October 25th at 7:00 a.m. The registration fee for IEEE members prior
to
October 8th is $395.00 and after October 8th is $415.00; non-members
prior
to October 8th is $500.00 and after October 8th is $550.00; for One Day
registration is $250.00; Students and IEEE Life members is $200.00. The
fee
includes the conference digest, refreshment breaks, luncheons, and a
Monday
evening welcoming reception.

Walk-in registrations will be accepted only on a space-available basis.

Tour of Kyocera America, Inc. Facility

Kyocera America, Inc., San Diego, California, is the world 92s #1
producer of
metallized ceramic packages for radio frequency and microwave devices, a
technology that is essential to wireless telecommunications. KAI also
offers
a complete line of multilayer ceramic and organic packages for
semiconductors
ranging from the latest computer chips to ASICS and mainframe
processors. To
complement these products, KAI offers state-of- the-art flip chip and
wire
bond packaging services and a full range of plating services.

A tour of the facility is being offered on Tuesday from 4:00 to 6:00
p.m. If
you are interested in this tour, be sure to mark the appropriate box on
the
registration form.

Luau, Hawaiian Feast , will be given on Tuesday evening, October 27,
1999,
from 7:00 to 9:30 p.m. on the North Beach of the Catamaran Resort
Hotel. The
cost for this is $45.00 per person, which includes food and beverages.

Accommodations

The Catamaran Resort Hotel, 3999 Mission Blvd., San Diego, CA 92109,
phone
619- 539-8700, fax 619-488-0901, is holding a block of 100 rooms for
participants at a special rate of $135.00 single and $145.00 double
occupancy
plus 10.5% tax. There are an additional 35 rooms being offered at
$99.00
plus 10.5% tax single or double occupancy, on a first come basis.
Reservations must be made by September 23, 1999 to receive these rates.
After this time reservations will be accepted on a space available basis
only. Please be sure to mention you are attending the EPEP '99
Conference.

Additional Information

Contact the conference co-chairs:

M. Swaminathan - email: madhavan.swaminathan@ece.gatech.edu phone:
404-894-3340, fax: 404-894-9959

R. Kaw - e-mail: ravi_kaw@hp.com phone: 650-857-8452, fax: 650-852-8676

or conference administrator:

P. Baltes - e-mail: epd@engr.arizona.edu
phone: 520-621-3054, fax: 520-621-1443

Conference Web Page

Updated information on the conference can also be found on the following
web
pages:

http://intermix.engr.arizona.edu/~epd/#EPEP
http://www.cpmt.org/conf/epep99/index.html

Directions to the Catamaran Resort Hotel

For those flying in - the hotel can be reached via the Cloud 9 Shuttle.
After claiming luggage, follow the signs to Ground Transportation and
proceed
to the
93Shuttle For Hire 94 curb and ask the Transportation Coordinator for
Cloud
9 Shuttle by name.


Sunday, October 24, 1999

Aviary Foyer

7:30 - 8:30 a.m. Registration for Short Courses 1, 2, 3, 4

9:00 a.m. - 5:00 p.m. Registration for Short Courses 5, 6, 7, 8 and
Meeting

Toucan Room

8:30 a.m. - 12:30 p.m. SHORT COURSE 1 - High-Speed Digital
Interconnect

Measurements and Modeling
Steven Corey and Dima Smolyansky, TDA Systems
Macaw Room

8:30 a.m. - 12:30 p.m. SHORT COURSE 2 - Recent Progress in Modelling
and
Simulation of High-Speed Interconnects
Michel Nakhla, Carleton University, Canada

Cockatoo Room

8:30 a.m. -12:30 p.m. SHORT COURSE 3 - Fast Computation of Capacitance

Matrices of Complex Interconnect Structures in Deep
Submicron Range
Raj Mittra, Pennsylvania State University

Rousseau Center East

8:30 a.m - 12:30 p.m. SHORT COURSE 4 - Characterization of Microwave

Packages
Tapan K. Sarkar, Syracuse University

Toucan Room

2:00 - 6:00 p.m. SHORT COURSE 5 - High-Frequency Measurement
Techniques for Characterization of Electronic
Packaging
Luc Martens, University of Gent, Belgium


Macaw Room

2:00 - 6:00 p.m. SHORT COURSE 6 - Power Distribution Challenges
in the New Millennium
Istvan Novak and Larry D. Smith, SUN Microsystems, Inc..


Cockatoo Room

2:00 - 6:00 p.m. SHORT COURSE 7 - Development of SPICE-
Compatible Transmission Line Models For
High-Speed Interconnections
Andreas C. Cangellaris and Jos E9 Schutt-Ain E9.
University of Illinois at Urbana-Champaign

Rousseau Center East

2:00 - 6:00 p.m. SHORT COURSE 8 - Design of High-Speed
Electrical Interconnects
Dale Becker, IBM Corporation and
Paul Franzon, North Carolina State University


Monday, October 25, 1999

Aviary Foyer

7:00 - 8:00 a.m. Registration

Kon Tiki Foyer

7:00 - 8:00 a.m. Continental Breakfast

Kon Tiki Ballroom

8:00 - 8:30 a.m. Introduction/Welcome

8:30 - 9:30 a.m. Session I - Plenary

Session Chair: Madhavan Swaminathan, Georgia Institute of Technology

Interconnect Limits on Gigascale Integration (KEYNOTE PAPER)
James D. Meindl, Georgia Institute of Technology, USA

Electronic Packaging For Microwave Multichip Modules (KEYNOTE PAPER)
Andrew J. Piloto, Kyocera America, Inc., USA

Kon Tiki Ballroom

9:30 - 10:40 a.m. Session II - System Design Issues I

Session Chair: Robert Frye, Lucent Technologies

Challenges (and Successes) in Packaging an Eight Way Service (INVITED)

Tom Aldridge, Intel Corp., USA

Physical Layer Design of a 1.6 GB/s DRAM Bus
Alfredo Moncayo, Saad Hindi, Ching-Chao Huang, Ravi Kollipara, Haw-Jyh
Liaw,
David Nguyen, Don Perino, Ali Sarfaraz and Chuck Yuan, Rambus, Inc.,
USA; Michael
Leddige, Jim McCall, Xang Moua and Joe Salmon, Intel Corp., USA

Implementation Considerations for RAMBUS 99-based Systems
Robert J. Evans, Jay Diepenbrock and Robert Sharrar, IBM Corp., USA

Toucan/Macaw Room

10:40 - 11:10 a.m. Break - Refreshments

Kon Tiki Ballroom

11:10 a.m. - 12:50 p.m. Session III - System Design Issues II

Session Chair: Moises Cases, IBM Corporation

Noise Verification Across 3 Levels of Packaging Hierarchy for the IBM

G5/G6 Mainframes
H. Smith, S. Kuppinger, P. Venkatachalam and W. Beker, IBM Corp., USA

Noise Measurements on Power4 Test Chip
Anand Haridass, Norman James and Bradley McCredie, IBM Corp., USA

Half-conductive Coupling for Chip-to-Chip Connections
W. Pan, C. De Tandt, F. Devisch, R. Vounckx and M. Kuijk, U of
Brussels,

Belgium

RF Interconnect for Multi-Gbit/sec Board-Level Clock Distribution -
(Student Paper)
Woonghwan Ryu, Hyungsoo Kim, Seungyoung Ahn, Namhoon Kim, Baekkyu
Choi and Joungho Kim, KAIST, Korea

Operating Frequency Trends for High Performance Off-Chip Buses
George A. Katopis, IBM Corp., USA

North Beach

1:00 - 2:00 p.m. Lunch (for Meeting attendees and guests with
tickets)


Kon Tiki Ballroom

2:00 - 3:40 p.m. Session IV - On Chip Interconnections

Session Chair: Paul Franzon, North Carolina State University

On-Chip Wiring Design Challenges for GHz Operation (INVITED)
A. Deutsch, H. Smith, G.V. Kopcsay, D.C. Edelstein, P.W. Coteus,
IBM Corporation, USA

Reliability and Performance Tradeoffs in the Design of On-Chip Power
Delivery
and Interconnects (INVITED)
Gregory F. Taylor, Tawfik Arabi, Hans Greub, Richard Muyshondt, alicia
Manthe and
Payman Aminzadeh, Intel Corp., USA

Impact of Cross-over Lines on Delay Time of Two Parallel Global Wires
Sangwoo Kim, Sun Microsystems, USA; Chi Shih Chang, Sematech, USA; Dean

Neikirk, U of Texas at Austin, USA

Asymptotically Zero Power Dissipation Gigahertz Clock Distribution
Networks
(Student Paper)
Payman Zarkesh-Ha and James D. Meindl, Georgia Institute of Technology,
USA

Toucan/Macaw Room

3:40 - 4:10 p.m. Break - Refreshments

Kon Tiki Ballroom

4:10 - 5:30 p.m. Session V - Measurement

Session Chair: Dylan Williams, National Institute of Standards and
Technology

Picosecond Time-Domain Photoconductive Sampling Method For Measuring
Guided and Free-Space Pulse Propagation
Joungho Kim, Jongjoo Lee, Heeseok Lee, Woopoung Kim and Jaeyoung Ryu,
KAIST, Korea

Limitations Due to Systematic Phase Errors on the Extraction of Loss
Tangent
46rom Micronsized Transmission Line Test Structures (Student Paper)
R.J. Friar and D.P. Neikirk, U of Texas at Austin, USA

Parameter Extraction for Circuit Models of Electronic Packages Without

Optimization
Luc Martens, U of Gent, Belgium; Stefaan Sercu, Framatome Connectors
International,
Belgium

Electrical Characterization of S/390 MCM Packages from S-Parameter
Measurements below 3 GHz
Faiez Ktata, Uwe Arz and Hartmut Grabinski, U of Hannover, Germany


Kon Tiki Ballroom

5:30 - 6:30 p.m. Session VI - Modeling I

Session Chair: Andreas Cangellaris, University of Illinois at Urbana
Champagne

Domain Decomposition Approach for Capacitance Computation of
Non-orthogonal Interconnect Structures
Vladimir Veremey and Raj Mittra, Pennsylvania State U, USA

Improved Global Rational Approximation Macromodeling Algorithm for
Transient Simulation of Interconnects - (Student Paper)
Mark Elzinga, Kathleen Virga and John L. Prince, U of Arizona, USA

Application of Subspace Projection Approaches for Reduced-Order
Modeling of Electromagnetic Systems - (Student Paper)
Tingdong Zhou, Steven L. Dvorak and John L. Prince, U of Arizona, USA

Toucan/Macaw Room

7:00 - 8:30 p.m. Session VII - Open Forum (Posters)

Session Chair: Paul A. Baltes, The University of Arizona

Numerical Analysis of Surface Waves on a Grounded Dielectric Plane
Using
the
Finite Difference Time Domain Method
Christian Schuster and Wolfgang Fichtner, Swiss Federal Institute of
Technology,
Switzerland

Modeling the Effects of Non-Linear Materials in De-Coupling
Components of Digital Systems
George Cokkinides and Benjamin Beker, U of South Carolina, USA

Power Distribution Modeling and Decoupling of Multilayer Printed
Circuit
Board
Jaya Bandyopadhyay, IBM Corp., USA

Electrical Performance of Buried Capacitors in Multi-layered PCBs
An Madou and Luc Martens, U of Gent, Belgium

Precise Chip and Package 3D Capacitance Simulations of Realistic
Interconnects
Using A General Purpose FEM-Tool
Andreas Hieke, Infineon Technologies Corp., USA

RF Characterization of Low Cost MCM-D Substrates, Manufactured on Large

Area Panels
Didier Cottet, Michael Scheffler, Janusz Grzyb, Benedikt Oswald and
Gerhard Tr F6ster,
ETH Zurich, Switzerland

Validation of Integrated Capacitor-Via-Planes Model
Yuan-Liang Li, David G. Figueroa, Teong Guan Yew and Chee Yee Chung,
Intel Corp.,
USA

High Performance Socket Characterization Technique for Microprocessors

David G. Figueroa, Chee Yee Chung, Michael D. Cornelius, Teong Guan Yew
and Yuan-
Liang Li, Intel Corp., USA

Achieving 800 MT/s Performance with PGA370 Socket
Chee-Yee Chung, Intel Corp, USA; Alex Waizman, Intel Corp., Israel

An Accurate and Complete Frequency Dependent Transmission Line
Characterization Using S-Parameter Measurements
Thomas-Michael Winkel, IBM Entwicklungs GmbH, Germany; Lohit Sagar
Dutta, U of Hannover, Germany

Transmission Link Radiation: Localized Defect Contribution
Edson Martinod, Pascal Nadeau, No EBl Feix, Mich E8le Lalande-Guionie,
Alain Reineix and
Bernard Jecko, IRCOM CNRS UMR, France

Power Plane Decoupling Strategy for High Speed Processor Boards
Tanmoy Roy and Larry Smith, Sun Microsystems Inc., USA


Tuesday, October 26, 1999

Kon Tiki Foyer

7:00 - 8:00 a.m. Continental Breakfast

Kon Tiki Ballroom

8:00 - 9:30 a.m. Session VIII - Power Distribution

Session Chair: Tawfik Arabi, Intel Corporation

Simultaneous Switching, Noise, and Reliability Analysis of VLSI Core
Logic
(INVITED)
Ibrahim N. Hajj, University of Illinois at Urbana-Champaign, USA

Modeling and Transient Simulation of Planes in Electronic Packages for
GHz
Systems (Student Paper)
Nanju Na and Madhavan Swaminathan, Georgia Institute of Technology, USA


Accuracy Considerations of Power-Ground Plane Models
Istvan Novak, SUN Microsystems, Inc., USA

Computation of the Frequency Response of Multiple Planes in Gigahertz
Packages
and Boards (Student Paper)
Jinseong Choi and Madhavan Swaminathan, Georgia Institute of
Technology,
USA

Toucan/Macaw Room

9:30 - 10:00 a.m. Break - Refreshments

Kon Tiki Ballroom

10:00 - 11:30 a.m. Session IX- SSN

Session Chair: John Prince, The University of Arizona

Simultaneous Switch Noise and Power Plane Bounce for CMOS Technology
(INVITED)
Larry Smith, Sun Microsystems Inc., USA

Modeling of Simultaneous Switching Output by Equivalent Source
Impedance

(Student Paper)
R.D. Lutz, A. Weisshaar and V.K. Tripathi, Oregon State U, USA: T.
Arabi
and
A. Lee, Intel Corp., USA

Off-Chip Delta-I Noise Modeling and Measurement Methodology
Nam Pham and Moises Cases, IBM Corp., USA; James Nissen, Motorola
Corp.,
USA

Design and Performance Evaluation of Chip Capacitors on Microprocessor

Packaging
Teong-Guan Yew, Yuan-Liang Li, Chee-Yee Chung and David G. Figueroa,
Intel Corp.,
USA


Beach North

11:30 - 12:30 p.m. Lunch (for Meeting attendees and guests with
tickets)


Kon Tiki Ballroom

12:30 - 1:50 p.m. Session X - Transmission Line Modeling

Session Chair: Ken Lee, Hewlett Packard

Characteristic Impedance of Microstrip on Silicon
Dylan F. Williams and Bradley K. Alpert, National Institute of
Standards
and
Technology, USA

Equivalent Circuit Modeling of Single and Coupled On-Chip Interconnects

on Lossy Silicon Substrate
J. Zheng, Y.-C. Hahm, A. Weisshaar and V.K. Tripathi, Oregon State U,
USA

Enhanced Skin Effect for Partial Element Equivalent Circuit (PEEC)
Models
Karen M. Coperich, U of Illinois Urbana-Champaign, USA: Albert E.
Ruehli,
IBM Research Division, USA: Andreas Cangellaris, U of Illinois Urbana-

Champaign, USA

Study of Meander Line Delay in Circuit Boards
Barry J. Rubin and Bhupindra Singh, IBM Corp., USA

Toucan/Macaw Room

1:50 - 2:10 p.m. Break - Refreshments


Kon Tiki Ballroom

2:10 - 3:30 p.m. Session XI - Emissions

Session Chair: Dale Becker, IBM Corporation

Radiated Emission from Pin-fin Heat Sink Mounted on an EBGA Package
Pingyu Qu, Mahadevan K. Iyer and Youlin Qiu, Institute of
Microelectronics,
Singapore

Methods to Reduce Radiation from Split Ground Plane Structures
Tamir E. Moran, Kathleen L. Virga, Gerardo Aguirre and John L. Prince,

U of Arizona, USA

Distributed Effects of a Gap in Power/Ground Planes
Dah-Weih Duan, Barry J. Rubin and J.H. Magerlein, IBM Corp., USA

A Novel Time Domain Algorithm for Field Excited Lossy Transmission
Lines

Petra Nordholz and Faiez Ktata, U of Hannover, Germany

4:00 - 6:00 p.m. Buses leave for Tour of Koyocera America, Inc.,
Facility

Beach North

7:00 - 9:30 p.m. Luau Dinner


Wednesday, October 27, 1999

Kon Tiki Foyer

7:00 - 8:00 a.m. Continental Breakfast

Kon Tiki Ballroom

8:00 - 9:10 a.m. Session XII- Microwave/RF Packaging I

Session Chair: Robert Jackson, University of Massachusetts

An Integrated Environment for the Simulation of Electrical, Thermal and

Electromagnetic Interactions in High-Performance Integrated Circuits
(INVITED)
Hector M. Gutierrez, Florida Institute of Technology, USA: Carlos E.
Christoffersen, North Carolina State U, USA; Michael B. Steer, The U of
Leeds,
UK

Toward a Novel Planar Circuit Compatible Silicon Micromachined
Waveguide
-
(Student Paper)
James P. Becker and Linda P.B. Katehi, U of Michigan, Ann Arbor, USA

77GHz Band Surface Mountable Ceramic Package
Shinichi Koriyama, Kenji Kitazawa, Hidehiro Minamiue and Mikio Fujii,
Kyocera Corp.,
Japan

Kon Tiki Ballroom

9:10 - 10:10 a.m. Session XIII - Microwave/RF Packaging II

Session Chair: Chong Park, Kyocera America, Inc.

Design Rule Development for Microwave Flip Chip Applications
Daniela Staiculescu, Joy Laskar, Georgia Institute of Technology, USA;
John Mather,
Rockwell Collins, USA

High-Performance Silicon MMIC Interconnect for Millimeter Wave Wireless

Communication
Juno Kim, Yongxi Qian, Guojin Feng, Pingxi Ma, M. Frank Chang and
Tatsuo
Itoh, U of
California, Los Angeles, USA

Simulation of Embedded RF Circuits Using Macromodels and Synthesized
Equivalent Circuits - (Student Paper)
Kwang Lim Choi and Madhavan Swaminathan, Georgia Institute of
Technology,
USA

Kon Tiki Foyer

10:10 - 10:30 a.m. Break - Refreshments

Kon Tiki Ballroom

10:30 - 12:20 a.m. Session XIV - Modeling II

Session Chair: Ravi Kaw, Hewlett Packard

On the Chicken-and-Egg Problem of Determining the Effect of Crosstalk
on

Delay in Integrated Circuits - (INVITED)
Sachin S. Sapatnekar, U of Minnesota, USA

Laguerre-SVD Reduced Order Modeling
Luc Knockaert and Daniel De Zutter, INTEC-IMEC, Belgium

Latency Insertion Method for the Fast Simulation of Interconnection
Networks
Jos E9 E. Schutt-Ain E9, U of Illinois at Urbana-Champaign, USA

A Fast Simulation Method for Single and Coupled Lossy Lines with
Frequency-
Dependent Parameters Based on Triangle Impulse Responses
Zhaoqing Chen, Wiren Dale Becker and George Katopis, IBM Corp., USA

Efficient and Accurate Extraction of Frequency-Dependent Resistance and

Inductance Parameters of Interconnects
Wei Wang, Jiayuan Fang and Yuzhe Chen, U of California at Santa Cruz,
USA

Kon Tiki Ballroom

12:20 - 12:30 p.m. Closing Remarks

Beach North

12:30 - 1:30 p.m. Lunch (for Meeting attendees and guests with
tickets)

Monday, October 25, 1999

7:00 - 8:00 am Registration & Continental Breakfast

8:00 - 8:30 am Introduction/Welcome

8:30 - 9:30 am Plenary

9:30 - 10:40 am System Design Issues I

10:40 - 11:10 am Break - Refreshments

11:10 - 12:50 pm System Design Issues II

1:00 - 2:00 pm Lunch

2:00 - 3:40 pm On Chip Interconnections

3:40 - 4:10 pm Break - Refreshments

4:10 - 5:30 pm Measurement

5:30 - 6:30 pm Modeling I

7:00- 8:30 pm Open Forum (Posters)

Tuesday, October 26, 1999

7:00 - 8:00 am Continental Breakfast

8:00 - 9:30 am Power Distribution

9:30 - 10:00 am Break - Refreshments

10:00 - 11:30 am SSN

11:30am - 12:30 pm Lunch

12:30 - 1:50 pm Transmission Line Modeling

1:50 - 2:10 pm Break - Refreshments

2:10 - 3:30 pm Emissions

4:00 - 6:00 pm Tour of Kyocera America, Inc.
7:00 - 9:30 pm Luau Dinner

Wednesday, October 27, 1999

7:00 - 8:00 am Continental Breakfast

8:00 - 9:10 am Microwave/RF Packaging I

9:10 - 10:10 am Microwave/RF Packaging II

10:10 - 10:30 am Break - Refreshments

10:30 - 12:20 am Modeling II

12:20 - 12:30 pm Closing Remarks

12:30 - 1:30 pm Lunch



SHORT COURSE 1
Sunday, October 24, 1999 from 8:30 a.m. to 12:30 p.m.

High-Speed Digital Interconnect Measurements and Modeling

Lecturers
Steven Corey and Dima Smolyansky, TDA Systems

Objective

The goal of this short course is to address important issues of
measurements
and equivalent circuit model extraction for the interconnects in the IC
packages, and to assist signal integrity engineers in choosing the most
appropriate modeling and simulation tools and techniques for their
designs.
This goal is accomplished by looking at the interaction between model
and
simulator and how it may be used to the designer 92s advantage. Both
time
and frequency domain measurements are discussed, and the model
extraction and
model verification techniques based on these measurements are presented.

Probing and fixturing issues, which are critical to the measurement
accuracy,
are addressed. The role of E&M standard SPICE-type simulators in the
model
verification are discussed.

Content

1 Why interconnects are important: industry trends and consequences
2. Interconnect issues in detail
3. Effective simulation and modeling
4. Measurement-based modeling approach
5. Basics of measurements: TDR and VNA
6. Measurement probing and fixturing
7. Interconnect modeling
8.1 From TDR measurements
8.2 From VNA measurements
9. Examples

Who Should Attend

The course is designed for engineers and researchers who work on
interconnect
characterization and signal integrity design and who are interested in
understanding how
to perform accurate repeatable measurements of interconnects, and learn
about
interconnect modeling and model verification techniques. It is
intended
for engineers
who would prefer to view circuit simulators, and time and frequency
domain
measurement instruments as flexible tools rather than as mysterious
black boxes.
Participants will emerge with an improved rationale for choosing
modeling and
simulation solutions.


Instructors

STEVEN COREY is responsible for Research and Development work at TDA
Systems.
He has been doing research on interconnect characterization and
modeling
since 1993 and
has published a number of papers in this area. During 1994-1997, Dr.
Corey worked on
applications solutions and did development work for Tektronix IPA-510
Interconnect
Parameter Analyzer, which used TDR/TDT measurement techniques to
extract
electrical
models of interconnects. He is an IEEE member since 1996. He holds
the
Ph.D. degree
from the University of Washington. His research interests are in
automatic measurement-
based model generation.

DIMA SMOLYANSKY is a Product Marketing Engineer at TDA Systems. Mr.
Smolyansky has been in the instrumentation and measurement industry for
8 years,
working with high-speed time domain reflectometry oscilloscopes and
frequency domain
network analyzers. He has worked as an RF/Microwave Applications
Engineer at
Cascade Microtech; characterization engineer at IMS; signal integrity
engineer at Intel,
and a design engineer at Performance Oscilloscopes Division at
Tektronix. During his
professional career, Mr. Smolyansky has accumulated significant
experience in the area
of high-speed digital interconnect measurements and modeling. He has
published a
number of papers and taught short courses on interconnect measurements
and modeling,
including the short course on interconnect measurements at EPEP'95. Mr.
Smolyansky is
an IEEE member since 1992. He holds the M.S.E.E. degree from Oregon
State University
and the Engineer Diploma (M.S.) degree from Kiev Polytechnic Institute.


SHORT COURSE 2
Sunday, October 24, 1999 from 8:00 am to 12300 p.m.

Recent Progress in Modelling and Simulation of High-Speed Interconnects


Lecturer

Michel Nakhla, Carleton University, Canada

Objective

The intense drive for signal integrity has been at the forefront of
rapid and
new development in CAD algorithms. With increasing demands for high
signal
speeds coupled with a decrease in feature size, interconnect effects
such as
signal delay, distortion and crosstalk become the dominant factors
limiting
overall performance of VLSI systems. On the other hand, interconnect
structures can be diverse and present at any of the hierarchical
packaging
levels including integrated circuits, printed circuit boards, multi-chip
modules and backplanes. If not considered during the design stage,
interconnect effects can cause logic glitches and signals distortion.
Since
extra iterations in the design cycle are costly, accurate prediction of
these
effects is a necessity in high- speed designs. Although conventional
CAD
tools such as SPICE are used routinely by many engineers for analog
simulation and general circuit analysis, these tools do not handle
adequately
the new emerging challenges of interconnect effects. This led to
intense
research during recent years to develop efficient techniques for
accurate
signal integrity analysis associated with high-speed interconnects.

Recently proposed model-reduction techniques, such as Asymptotic
Waveform
Evaluation (AWE), Complex-Frequency Hopping (CFH) and Krylov space-based

methods have proven useful in the analysis of large interconnect
structures
containing lossless and lossy high-speed interconnects with linear or
nonlinear terminations. At a CPU cost of a little more than one DC
analysis,
these techniques are 2-3 orders of magnitude faster than conventional
methods.

This tutorial presents an overview of interconnect modelling/simulation
strategies with emphasis on diverse algorithms and applications of
model-reduction techniques. The underlying basic concepts will be
demonstrated by several practical examples.

Content

The first part of the course covers the basic principles of circuit
simulation. The second part focuses on issues and analysis techniques
related to high-speed circuits and interconnects. Various interconnect
models will be considered, including RC/RLC lumped, distributed,
full-wave,
measured and EMI-based. The basic principles of model- reduction
techniques
will be described in details together with their extension to some
frequently-encountered practical situations, such as simulation of
subcircuits characterized by measured S-parameters and
frequency-dependent
components (e.g. resulting from skin and proximity effects).
Applications
cover wide spectrums of implementation hierarchy including chip,
multichip
modules, packages and printed circuit boards.

Who Should Attend

The tutorial is intended for developers of CAD tools and for circuit
designers as well. It is presented in an easy to understand style and
prior
background in this area is not required.

Instructor

MICHEL NAKHLA is a Professor of Electrical Engineering at Carleton
University. He received the M.A.Sc. and Ph.D. degrees in electrical
engineering from University of Waterloo, Ontario, Canada, in 1973 and
1975,
respectively. From 1976-88 he was with Bell-Northern Research, Ottawa,
Canada, as the senior manager of the computer-aided engineering group.
In
1988, he joined Carleton University, Ottawa, Canada, where he is
currently
the holder of the Computer-Aided Engineering Senior Industrial Chair
established by NORTEL Networks and the Natural Sciences and Engineering
Research Council of Canada. He is the founder of the high-speed CAD
research
group at Carleton University. He serves as technical consultant for
several
industrial organizations and the principal investigator for several
major
sponsored research projects. He has authored and co-authored over 150
technical papers and two books on high-speed circuits and interconnects.

Dr. Nakhla is a fellow of the IEEE and is on the editorial board of
several
international journals. He is a frequent invited speaker on the topic of
high-speed interconnects.

SHORT COURSE 3 Sunday, October 24, 1999 from 8:30 am to 12:30 p.m.

Fast Computation of Capacitance Matrices of Complex Interconnect
Structures
in the Deep Submicron Range

Lecturer

Raj Mittra, Pennsylvania State University

Objective

The objectives of this short course are: (I) to review the Boundary
element,
Monte Carlo and Finite Difference methods for computing the capacitance
matrices of complex interconnect structures; and, (II) to discuss
various
techniques for speeding up the computation as well as for handling large
problems that are highly memory intensive. In particular, the Domain
Decomposition scheme for interconnects with multiple nets that are too
large
to be analyzed by suing conventional methods because of cpu memory
limitations is presented.

Content

1. Overview of VLSI Interconnects 2. Brief review of signal integrity
issues 3. Techniques of Capacitance Computation ? Boundary Element
Method
(BEM); Refinements of the BEM for enhancing the computational efficiency
?
Monte Carlo Method for fast computation of self capacitance ? Finite
Difference (FD) Method for general interconnect structures, including
wraparound dielectrics; recent developments in FD mesh truncation ?
Capacitance computation of typical interconnect components, including
crossovers, vias, bends, etc. ? Domain Decompostion Method ?
Application of
Domain Decomposition scheme to capacitance computation for complex
interconnects with multiple nets and of large structures that are memory
intensive ? Illustrative examples

Who Should Attend

Chip designers interested in estimating delay, crosstalk, signal
integrity
and electromigration problems and engineers interested in developing
some
background in these areas.

Instructor

RAJ MITTRA is a Professor of Electrical Engineering at the Pennsylvania
State
University, and the Director of the Electromagnetic Communication
Laboratory. He has directed many short course on Electronic Packaging
and
Computation electromagnetics, both in the U.S. and in Europe, and has
offered
on-site seminar series at several industrial locations, include GTE
Network
Systems, Cray Research, DEC, IBM and Intel. He has authored and
co-authored
over 500 research papers and 30 textbooks and monographs. He has served
the
IEEE AP-S Society as a National Distinguished Lecturer, as President,
and as
an Editor of the IEEE Transactions on Antennas and Propagation. He also
heads RM Associates, a company that provides consulting services to many
government and industrial organizations.

SHORT COURSE 4 Sunday, October 24, 1999 from 8:30 to 12:30 p.m.

Characterization of Microwave Packages

Lecturer

Tapan K. Sarkar, Syracuse University

Objective

In recent years there has been an increased interest in understanding
the
physical mechanism of signal propagation on multiconductor transmission
systems connecting fast switching digital devices and high frequency
analog
devices. Examples are MMIC, Printed Circuits and Hybrid Devices. The
course
is designed to increase the computational speed and efficiency of the
analysis tools so that electrically large problems can be solved
utilizing
limited resources. One method to accomplish this is the Model Based
parameter estimation method. This technique is not an ad hoc curve
fitting
technique. There is a scientific methodology on how that is
accomplished and
a way to automatically determine the quality, adequacy and suitability
of the
data. Numerical examples will be presented to illustrate the efficiency
and
accuracy of the technique.

Who Should Attend

Those electrical engineers and physicists involved in the analysis and
design
of monolithic, hybrid, printed circuits and high-speed interconnects for
computers and microwave applications.

Instructor

TAPAN K. SARKAR is a Professor of Electrical Engineering and Computer
Science
at Syracuse University. He has done extensive research for various
computer
and microwave companies in the analysis and design of printed circuits.
He
is a professional engineer the State of New York. He is a Fellow of the
IEEE
and recently was awarded Docteur Honoris Causa from the University of
Blaise
Pascal (France).

SHORT COURSE 5 Sunday, October 24, 1999 from 2:00 to 6:00 p.m.

High-Frequency Measurement Techniques For Characterization of Electronic

Packaging

Lecturer

Luc Martens, University of Gent, Belgium

Objective

The objective of the course is to explain the basic and advanced
principles
of high- frequency measurements applied to electronic packaging.
Especially
problems related to the high-frequency characterization will be
addressed.
Practical solutions will be proposed and illustrated with up-to-date
examples. At the end of the course, the participant should be able to
design
or select the best test fixture and measuring instrument for his or her
application and to perform accurate high-frequency measurements. It
will
also be clear that circuit-modeling starting from the measurements is an
essential part of the characterization process. The discussion of
advantages
and drawbacks of different measurement-based modeling algorithms will
enable
the participant to select the appropriate method.

Content

The course is based upon the practical experience of the instructor and
his
team in basic and advanced measurement techniques and in applications of
the
techniques to a variety of modern interconnections, packages and
connectors.

The following topics will be covered:

? Basic high-frequency measurement techniques and instruments (vector
network
analyzer, time-domain network analyzer, impedance analyzer) ?
Calibration and
de-embedding ? Test fixtures, wafer and PCB probing techniques ?
Measurement
of signal integrity characteristics (reflection, delay, losses,
rise-time
degradation, crosstalk, switching noise) ? Measurement-based circuit
modeling
algorithms ? Application of the presented techniques to PCB and on-chip
interconnections, to connectors and to IC-packages

Instructor

LUC MARTENS received the M.Sc. degree in electrical engineering the
University of Gent (Belgium) in July 1986. From September 1986 to
December
1990 he was a research assistant at the Department of Information
Technology
(INTEC) of the same university. During this period, his scientific work
was
focused on the physical aspects of hyperthermic cancer therapy. This
work
led to a Ph.D. degree in December 1990. As of January 1991, he is a
member
of the permanent staff of the Inter-university Micro- Electronics Center
(IMEC) and is responsible for the research on characterization of
packaging
technologies with respect to their high-frequency and EMC behavior and
for
the research on experimental modeling of active devices at INTEC. In
April
1993 he became a professor in electrical applications of
electromagnetism at
the University of Gent.

His team of more than 10 researchers develops innovative measurement
techniques and circuit modeling algorithms for characterization of
electronic
packaging. The techniques have been applied to many packaging
technologies
through cooperation with many industrial partners, such as Alcatel
Telecom
and Framatome Connectors International. He is author or co-author of
more
than 80 publications in the field of characterization of electronic
packaging. He has written a book, 93High-Frequency Characterization of
Electronic Packaging 94, (ISBN 0-7923-8307-9) which was published by
Kluwer
Academic Publishers in 1998.

Short Course 6 Sunday, October 24, 1999 from 2:00 to 6:00 p.m.

Power Distribution Challenges in the New Millennium

Lecturer

Istvan Novak and Larry D. Smith, Sun Microsystems, Inc.

Objective

After completing the course, participants should be able to make a
proper
choice of voltage regulator modules, decoupling inductors and bypass
capacitors, be able to select the proper PCB layout and stockup for
power
distribution, understand the tradeoffs of various modeling and
simulation
options, as well as be able to perform accurate measurements on the
power
distribution system.

Content

Overview of power-distribution requirements
trends of different supply voltage needs Power-distribution hierarchy
centralized vs. distributed Characteristics and modeling of voltage
regulator modules
transient requirements frequency-domain requirements averaged SPICE
models behavioral SPICE models Characteristics and modeling of
capacitors and inductors
ESR and ESL of capacitors: how low we can (or want to)go why and why
lossy inductors are useful Characteristics and modeling of power
planes
static capacitance and spreading inductance of plane pairs resonance
effects in planes modeling and simulation of power planes
Bypass-design methodologies based on local capacitors
requirements and connection of capacitors Bypass-design methodologies
based on local planes
requirements and design of planes Measurements of power-distribution
networks
required instrumentation time-domain measurements measurements of
very low impedance values

Participants receive reference list and free illustration software

Who Should Attend

System board and module designers who deal with low-voltage/high-power
and
high- speed digital electronics

Instructor

ISTVAN NOVAK is a Fellow of IEEE for his contributions to
signal-integrity
modelling, measurements and simulations and a signal integrity engineer
of
SUN Microsystems, Inc. working on high-speed serial and parallel buses,
interconnects, advanced packaging and power distribution. He is an
international consultant and instructor, with 27 years of experience in
the
field of high-speed and high-frequency circuits and systems. He has
been
teaching industry short courses through George Washington University,
Worcester Polytechnic Institute and Technion (Israel). He has been
advising
the European Laboratory for Particle Physics (CERN) on Signal-Integrity
and
EMC issues for Fibre Channel Data-Collection Systems of the Large Hadron
Collider. He worked and consulted for several companies in the computer
and
telecommunications industry, to do clock-and power-distribution
networks,
switching-mode converters as well as TTL, CMOS, and BTL backplanes up to
600
MB/s, PCI buses, and copper and optical interconnects in the GB/s
range. He
received his technical education from the Technical University of
Budapest,
and his Ph. D degree from the Hungarian Academy of Sciences. He
organized
and led the High Speed Technology Team at the Technical University of
Budapest, where his teaching activity covered transmission lines and
wave
propagation, EMC and signal-integrity issues of high-speed logic design,
and
communications. He holds several patents in the field of signal
integrity
and digital signal processing and published over one hundred technical
papers.

LARRY D. SMITH received the BSEE degree from Rose Hulman Institute of

Technology in 1975 and the MS degree in Material Science from the
University
of Vermont in 1983. After joining IBM in 1978, he worked in the areas
of
reliability, characterization, failure analysis, power supply and analog
circuit design, packaging and signal integrity. He has continued his
efforts
in signal integrity at Sun Microsystems since 1996. His current area of
concentration is design of power distribution systems.

Short Course 7 Sunday, October 24, 1999 from 2:00 to 6:00 p.m.

Development of SPICE-Compatible Transmission Line Models for High-Speed

Interconnections

Lecturers

Andreas C. Cangellaris and Jos E9 Schutt-Ain E9, University of Illinois
at
Urbana-Champaign

Objective

The aim of this short course is to present and discuss in detail the
application of multiconductor transmission line theory to the modeling
of
high-speed interconnections for chip, package, and board electrical
performance simulation. The focus of the presentation will be on the
following key issues: 1. The fundamentals of multiconductor
transmission
line (MTL) modeling of high-speed interconnections, and the types and
geometries of high-speed interconnections for which use of an MTL model
makes
sense. 2. The conditions under which frequency-dependent losses must be
taken into account, and the various modeling approaches used for the
extraction of frequency-dependent per-unit-length (p.u.l.) inductance
and
resistance matrices 3. Transmission line modeling of interconnections in
the
presence of crossing wires 4. Extraction of the transmission line
parameters
of interconnections through measurements 5. Methodologies of the direct
incorporation of transmission line models in SPICE

Content

? Multiconductor Transmission Line (MTL) Theory
1) TEM waves and MTL Equations 2) Per-unit-length Capacitance,
Inductance, Conductance and Resistance Matrices
3) The quasi-TEM approximation for MTLs in layered dielectrics 4)
Modal analysis of MTLs ? Overview of Methodologies for MTL
Parameter
extraction
1) Extraction of p.u.l. capacitance and inductance matrix for
loss-free lines
2) Extraction of p.u.l. conductance matrix for MTLs in lossy
substrates ? Modeling of MTLs with Frequency-Dependent Losses
1) Lossy conductors and skin effect 2) Extraction of p.u.l.
resistance, and inductance matrices 3) When is skin-effect
modeling
needed? ? SPICE-Compatible Models for MTLs
1) Discrete model based on distributed R,L,C,G equivalent circuits
2) Rigorous model for loss-free lines 3) Models for MTLs with
frequency-dependent losses ? Experimental Characterization of MTLs
1) Extraction of MTL parameters from measurements 2) Synthesis of
SPICE-compatible models from MTLs from measured data ? MTL Models
for Interconnects in Complex Media
1) Interconnects in the presence of crossing wires 2) Interconnects
in the presence of semiconductor substrates

Who Should Attend

This short course will be useful to signal-integrity engineers,
electronic
packaging engineers, and, in general, anyone interested in the
electrical
modeling and transient, SPICE-based simulation of high-speed
interconnections. In addition to a thorough discussion of the
fundamentals
of transmission line theory and its suitability and implementation to
interconnection modeling, the state of the art in experimental
characterization of high-speed interconnections, and the development of
SPICE- compatible models from measured data will be presented.

Instructors

ANDREAS C. CANGELLARIS is a Professor of Electrical and Computer
Engineering
at the University of Illinois at Urbana-Champaign. He holds a Ph.D. in
Electrical Engineering from the University of California, Berkeley.
Prior to
joining the University of Illinois faculty he was with the Department of
Electrical and Computer Engineering at The University of Arizona,
Tucson,
Arizona, for the period of September 1987 - August 1997.

Prior to that, he spent two years with the Electrical and Electronics
Engineering Department, General Motors Research Laboratories, Warren,
Michigan, working on electromagnetic compatibility and antenna design.
Professor Cangellaris has authored and co-authored over 100 scientific
journal and conference papers in the areas of computational
electromagnetics,
high-speed electronic packaging, and microwave engineering. Over the
past
ten years, he has supervised the development of electromagnetic software
tools for the electrical modeling of package parasitics and the
simulations
of pulse propagation in complex interconnect media for high-speed
electronics. He received the International Union of Radio Science
(URSI)
Young Scientist Award in 1993, and is an active member of the IEEE
Antennas
and Propagation, and IEEE Microwave Theory and Technology Societies. He
is
currently a member of the technical program committees for the IEEE
International Microwave Symposium and the Electronic Components and
Technology Conference. Also, he is on the Board of Directors of the
Applied
computational Electromagnetics Society, and was General Chair of the
1998
Conference on Electromagnetic Field Computation. Professor Cangellaris
is
the co-founder of the IEEE Topical Meeting on Electrical Performance of
Electronic Packaging, which is sponsored by the IEEE Microwave Theory
and
Techniques Society and the IEEE Components, Packaging and Manufacturing
Technology Society.

JOS C9 SCHUTT-AIN C9 (B.S. '81, MIT, M.S.'84, Ph.D. '88, UIUC) started
his
career as an Application Engineer at the Hewlett-Packard Microwave
Technology
Center in Santa Rosa, CA in 1981-1983 and was involved in the design and
testing of high-frequency. His work also included the modeling and
testing
of microwave bipolar transistors. During his graduate studies at UIUC
he
held summer positions at GTE Network Systems in Northlake, IL where he
conducted research in signal integrity in high-speed digital
telecommunication networks. He joined the faculty of the
Electromagnetic
Communication Laboratory in 1989 where he is currently an Associate
Professor
of Electrical and Computer Engineering at the University of Illinois.
Professor Schutt- Ain E9's interests include microwave theory and
measurements, electromagnetics, high- speed digital circuits,
solid-state
electronics, the design and simulation of multichip modules and
electronic
packaging.

Short Course 8 Sunday, October 24, 1999 from 2:00 to 6:00 p.m.

Design of High-Speed Electrical Interconnects

Lecturers

Dale Becker, IBM Corporation Paul Franzon, North Carolina State
University

Objective

The intent of this short course is to introduce the attendees to the
concepts
of designing electrical interconnects in the high density and high
frequency
chips and packages required for today 92s electronic systems. After
completing this course, the students should understand the key concepts
of
electrical interconnect design, including interconnect topologies,
factors
which degrade the interconnect performance, modeling and analysis, and
implementing a robust design.

Content

This course is based upon the practical experiences of the instructors
who
have applied the theoretical concepts to design and analyze
high-performance
systems.

The design at the chip, chip package, and PCB levels of packaging will
be
addressed.

The following topics will be covered:

? Overview of interconnect hierarchy ? Signal integrity and synchronous
design ? Interconnect decision making ? Layout and termination issues ?
Sources of noise and signal degradation ? Timing budget; Noise budget ?
Skin
effect and dielectric losses ? Reflection, crosstalk, simultaneous
switching
noise ? Modeling of transmission lines and discontinuities ? Model
fidelity ?
Extraction for modeling and analysis ? Using CAD tools

The theoretical background will be discussed, and the practical
implementation of the theoretical concepts will be emphasized.

Instructors

DALE BECKER received his Ph.D. in Electrical & Computer Engineering from
the
University of Illinois. He is currently a Senior Engineer in the Server
Group of IBM in Poughkeepsie, NY. He leads the MCM design team that
integrates and implements the multiprocessor design for IBM 92s large
server
platforms. Dr. Beckers 92 s current interests focus on the electrical
design
of the components that comprise a high-frequency CMOS processor system.
He
specializes in the application of electromagnetic numerical methods to
the
issues of signal integrity and simultaneous switching noise in
electronic
packaging, the measurement of these phenomenon, and the verification of
the
models.

PAUL FRANZON is a Professor in the Department of Electrical and Computer

Engineering at North Carolina State University. He has ten years of
experience in electronic systems design and design methodology research
and
development, including working at AT&T Bell Laboratories, and as the
founding
member of a communications company. Dr. Franzon 92s current research
interests focus on the design

sciences/methodology for high-speed packaging and interconnect, and also
for
high-speed and low-power chip design. He is a consultant to a number of
companies in these areas and has extensive experience in teaching
related
professional courses.

Registration Form

Participants are urged to register early and thereby help the organizers
with
planning.

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Short Course Registration Fee (Per Person/Per Course)

(COURSES DO NOT MEET REGISTRATION MINIMUM BY OCTOBER 8, 1999 WILL BE
CANCELLED)

Course Number 1 $250 $_______
Course Number 2 $250 $_______
Course Number 3 $250 $
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Course Number 4 $250 $
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Course Number 5

$250 $ _______ Course Number 6
$250 $ _______ Course Number 7
$250 $________ Course Number 8
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Meeting Registration Fee (Per Person) (includes digest, refreshment
breaks,
lunches, and reception)

IEEE members (prior to October 8)
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8) $500 $________ Non-members (after
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TUESDAY EVENING LUA (MUST REGISTER BY OCTOBER 8)

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Total Enclosed
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7F A tour of the Kyocera America, Inc. Facility is being offered on
Tuesday
afternoon, October 26, 1999, from 4:00 to 6:00 p.m. Participants
interested
in the tour should check here.

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sign
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