RE: [SI-LIST] : response to semiconductor I/O edge rates

tomda (tom_dagostino@mentorg.com)
Thu, 15 Jul 1999 14:26:06 -0700

To speak the obvious, if you have a 4 MHz circuit why are you using 100+MHz
parts? You can still buy older technology parts that have not had their
slew rates increased. If you are designing an ASIC then use the
appropriate driver for the slow nets.

Tom Dagostino

-----Original Message-----
From: Muranyi, Arpad [SMTP:arpad.muranyi@intel.com]
Sent: Thursday, July 15, 1999 11:38 AM
To: 'si-list@silab.eng.sun.com'
Subject: RE: [SI-LIST] : response to semiconductor I/O edge rates

I would like to reiterate an earlier response by someone.

With many chips one big problem is that even if the semiconductor vendors
go out of their way and put slew rate controlled buffers into their
products,
there is no way to tell how fast the product will actually run in a
particular
design. This is especially true for glue logic chips which can be used in
a
1 MHz system just as well as in a 100 MHz system. How should the IC vendor
adjust the slew rate then? It will have to be externally programmable
then,
which adds more design complexity, and will raise the cost of the part.

Are people be willing to pay that extra cost in large quantities? Even if
the answer is yes, an SI engineer will still be needed to determine
the optimal setting of the slew rate for the particular design.

Arpad Muranyi
Intel Corporation
========================================================================

-----Original Message-----
From: Roy Leventhal [mailto:Roy_Leventhal@mw.3com.com]
Sent: Thursday, July 15, 1999 8:47 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : respons to semiconductor I/O edge rates

All,

I have really appreciated the ongoing discussion about edge rates that my
original beef has kicked up and the many related topics it has opened up.

Lest we loose sight of my original beef it is this:

A consequence of shrinking feature size to get more on a die and faster
processing speeds is this: Edge rates have been kicked into warp speed:
This
has
lead most boards potentially having a signal integrity problem on every net
on
the board --> where the edge rate bears no relation - way too fast - to the
intended application it creates "make work" unneccesary problems that cuts
into
his/her chances of competitive success.

So long as SI engineers don't understand this and don't push back on their
suppliers to see if the problem can be fixed at the SOURCE, they don't
understand that they're hired to make a contribution, not engage in busy
work.

Roy

Roy

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