The EBD format does not support coupled connector parasitics, to my knowledge.
There is an IBIS subcommittee working on a pretty comprehensive connector
But, each path description in the pentium 2 processor EBD file has an LC
parasitic entry for an "SC242 CONNECTOR". So it appears to have single-pin
parasitics for one connector half built into the cartridge model. The README.txt
file for the Pentium 2 model does state that crosstalk is not modeled. If you have
a full Spice model for the mated connector pair, you may need to comment out
the "SC242 CONNECTOR" lines in the IBIS (in vi: ":%g/SC242 CONNECTOR/s/^/|/"),
so that these parasitics will not be double-counted. I'm not yet certain that
this will work, since those lines also have a Len parameter. Maybe someone else
could bail me out here.
To use your Spice connector model in SpecctraQuest you make a "skeleton"
IbisDevice model for the Slot 1 connector on the motherboard (SpecctraQuest
has a "Create Model" button to do this for you), and assign a PackageModel
containing your Spice subckt to it. Then SpecctraQuest will insert the
Spice PackageModel into the circuit when simulating nets that go through
the Slot 1 connector.
The difficult part is creating the PackageModel using the supplied Spice model.
I have done this a few times and had to wrestle with a basic lack of information
about the Spice model given to me. Which two nodes are for pin A1? Which is
the inside connection and which is the outside? Only the software that created
the Spice model knows, in most cases. A standard format would be nice (IMIC?).
I hope you get the info you need.
Kim Helliwell wrote:
> I face the following puzzle in running a signal integrity
> simulation on Pentium II board. I'm using SpecctraQuest
> and Signoise, in case this matters.
> I have a Pentium II IBIS model (which I converted to Cadence's
> .dml format). This model appears to model all the parasitics
> of the Slot 1 board in a lumped manner; I presume that the
> model includes parasitics up to the edge fingers. (Does anyone
> know different?)
> I also have a model of a Slot 1 connector in SPICE format. Quite
> aside from issues of how this model is to be used (I'm trying to
> get the answer to that from the supplier) is the issue of how to
> include the Slot 1 connector parasitics in the simulation. At
> first, I thought I could use a design link and treat the connector
> as a cable connecting the main board and the Slot 1 module, but I
> think that requires that I have the "board layout" of the Pentium
> module. The next thought was to treat the connector as a package, but
> this doesn't work since the Pentium II module is already a package
> model. So I'm left with adding the connector parasitics in some
> fashion to the existing Pentium II model. I just want to check
> that this is in fact the correct approach, or else find out whether
> I'm giving up too soon on one of the first two approaches mentioned,
> or whether there's another approach I haven't considered.
> I'm sure I'm not the only one facing this, so how are others
> solving it?
> Kim Helliwell
> Senior CAE Engineer
> Acuson Corporation
> Phone: 650 694 5030 FAX: 650 943 7260
> **** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****