Re: [SI-LIST] : response to semiconductor I/O edge rates

David Haedge (d-haedge@raytheon.com)
Mon, 19 Jul 1999 11:28:43 -0500

Roy Leventhal wrote:
>
> You guys keep hitting on Texas.
>
> Actually, Fairchild developed the planar process and heavily influence the whole
> specsmanship thing. Their ideas included making specs so wide you couldn't
> possibly miss and universal devices that would play in any application. Then
> crank the diffusion furnaces to just under melting temperature so you could slam
> the wafer boats in & out faster.

We were doing some timing delay simulations using SPICE models from that
that cave in Texas. Our loading was around 15pF and the data
book numbers spec'd at 15pF were about 1.0-1.5ns greater than the what
SPICE told us. We went round and round trying to find out which one was
right, had we made the right assumptions in SPICE, were we using the data
book numbers correctly, and so on. We finally found a guy in the cave that
told us the truth. His words to us: " Believe the SPICE results before you
believe what's on the data sheet, its all specsmanship. But don't expect
to see the data book numbers changed anytime soon."

David Haedge
Raytheon

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