I'm not an EE but I have some input into this.
What I try to always do is consider the line to line spacing.
If the spacing between conductors is established based on
noise margin budgets, then I always try to maintain that dielectric
thickness between signal layers as a minimum. (i.e., .006" line and
.006" space I would use a minimum of .006" dielectric between
signal layers.) This keeps the crosstalk coupling to a minimum.
Actual amount it changes the Zo, I don't really know. What I
listed above is a "rule of thumb" that was passed on to me from EMC
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When you have a PCB stackup that has a signal plane sandwiched between two
ground planes, you have stripline. Zo at this point is fairly easy to
Now, if you add a second signal layer in between the two ground planes, one
in the X direction and the other in the Y, you still have stripline
(asymetric), but now you have a bunch of traces crossing the path above (or
below) your signal layer. I understand this introduces crosstalk, but what
does it do to the characteristic impedance of your traces? Is the impedance
still controlled? Does it vary widely, or not have much effect at all?
I see a lot of stackups with this arrangement, and I wonder how Zo is
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