Re: [SI-LIST] : Edge Rates

D. C. Sessions (dc.sessions@vlsi.com)
Fri, 09 Jul 1999 09:52:44 -0700

"Peterson, James F (FL51)" wrote:
>
> What seems to complicate my perspective on these super-fast edge rates is
> how they are effected by the load of the circuit. I believe that, without
> loading, most edge rates are sub-nano, but once loaded, they do slow down.
> Do we use this effective edge rate in our analysis or the raw edge rate? It
> seems that raw edge-rates might be conservative in certain practical
> situations. The only way I see of getting more realistic numbers, that could
> be applied in t-line analysis, is to have a good simulator that generates a
> waveform based on the driver and its environment (trace, loads, etc.) while
> distributing and lumping where appropriate.

Loaded edge rates are only relevant at the load. The wave on the line is
the deep-sub-nanosecond one coming from the driver. The slow edge that
you're thinking of is the superposition of this edge with the capacitive
reflection from the load.

The difference is important for several reasons, but primarily for
crosstalk analysis both in the driving package and in trace coupling.

> -----Original Message-----
> From: Dr. Edward P. Sayre [mailto:esayre@nesa.com]
> Sent: Friday, July 09, 1999 9:10 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Edge Rates
>
> It has been an interesting set of developments over the last two years.
> Before we had one or two SI problems in a design, now every trace has the
> potential for SI problems.
>
> ed
> ======
> At 02:47 PM 7/8/99 -0700, you wrote:
> >I concur with Tom. It is highly unusual to see
> >a device these days that has an edge rate more
> >than 500 ps. This means that almost every pc
> >board trace must be considered a transmission line for
> >analysis purpose. Most devices manufactured today
> >also tend to have lower channel resistance than
> >necessary (10 to 25 ohms), which will cause severe
> >overshoot and ringback on unterminated nets.
> >
> >BTW, Tom also gives a great presentation with
> >a breakdown of the measured edgerate characteristics
> >of various devices.
> >
> >regards,
> >
> >scott
> >
> >
> >tomda wrote:
> >
> >> Assume 100 to 500 psec for the full transition for any modern logic
> family
> >> unless it has controlled edge rates.
> >>
> >> Tom Dagostino
> >>
> >> -----Original Message-----
> >> From: Ken Patterson [SMTP:ken.patterson@pathway-inc.com]
> >> Sent: Thursday, July 08, 1999 12:07 PM
> >> To: si-list@silab.eng.sun.com
> >> Subject: [SI-LIST] : Edge Rates
> >>
> >> I am a newcomer to signal integrity analysis and would like to know how
> >> to find out what the typical edge rates (i.e. rise and fall times) of
> >> some of the industry standard logic families are. These include FCT
> >> logic, SDRAMs and Syncburst SRAMs . I have an upcoming project that
> >> will use these devices and would loike to perform some signal integrity
> >> analysis.
> >>
> >> Ken Patterson
> >> Electronic Engineer
> >> ADC Broadband Communications/Pathway Division
> >> email:ken.patterson@pathway-inc.com
> >>
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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