RE: [SI-LIST] : Terminating a bidirectional bus

Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Tue, 4 May 1999 09:51:28 -0500

>I would like to know you opinion on this issue. I am interfacing a
>state of the art FPGA with a high speed synchronous SRAM device. Since
>the interface is bidirectional (the FPGA will read and write data to
>the memory) I was wondering what is is the best way to terminate this
>bus.

You could parallel-terminate both ends. You could series-terminate both
ends, keeping the resistors close to either device. Etc. There is no one
"best way."

> My intuition is that if the data lines are not very long, then a
>series termination near the FPGA end could have an effect similar to a
>series termination near the memory end when the memory is driving the
>bus.

Series termination at the end of a line doesn't do much.

If they aren't very long, you could go direct with no terminations.

Depends on the drive strengths on the two ends. If one is much weaker than
the other, that direction might need no termination while the other does.
Also depends on input structures (clamp diodes), and on how much transient
overshoot they can tolerate. Supposedly, some RAMs and FPGAs may lose their
state or their programming, given enough overshoot.

Regards,
Andy

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