You could parallel-terminate both ends. You could series-terminate both
ends, keeping the resistors close to either device. Etc. There is no one
> My intuition is that if the data lines are not very long, then a
>series termination near the FPGA end could have an effect similar to a
>series termination near the memory end when the memory is driving the
Series termination at the end of a line doesn't do much.
If they aren't very long, you could go direct with no terminations.
Depends on the drive strengths on the two ends. If one is much weaker than
the other, that direction might need no termination while the other does.
Also depends on input structures (clamp diodes), and on how much transient
overshoot they can tolerate. Supposedly, some RAMs and FPGAs may lose their
state or their programming, given enough overshoot.
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****