RE: [SI-LIST] : Via Capacitances ...

Denomme, Paul S. (Paul.Denomme@viasystems.com)
Tue, 13 Jul 1999 08:16:28 -0400

Dave,

This via is acting as mainly a capacitor when determining the
impedance of the line. In very thick boards such as backplanes when you
have multiple planes, there is added capacitance and inductance to the
signal line, however when determining impedance, the capacitance has a much
larger effect on the net results. Since Z=SQR(L/C), when you increrase the
capacitance of the line due to the via, the impedance decreases. Some ways
of minimizing the capacitance of the via hole is to remove unused pads on
the board as well as increasing the clearance of the power planes. In real
thick boards with many power planes, a via can well exceed 1pF of
capacitance.
As an example, if you have a thru hole board that has holes every
1.0 inches, the impedance of the trace will be greatly affected by the
capacitance on the via hole if you average the capacitance of the via hole
throughout the length of the signal line. Lets say the trace impedance is
75 ohms. The inductance of the trace is 11000pH/in. The capacitance is
1.95pF/in. If we place these numbers in the formula Z=SQR(L/C), we get an
impedance of 75.1 ohms. If you have a via that adds say 1pF of capacitance
and 450 pH of Inductance to the signal line and you average that over the
inch of signal line, you would end up with Z=SQR[(11000+450)/(1.95+1)] which
results in 62.3 ohms. So the thru holes can have a large effect on the
impedance of the trace. These numbers are only guesstimates from some
simulations and resultant backplanes that I have designed from the past. If
the numbers were not correct I apologize, but I do know that in a backplane
environment the thru-hole/via can have a large impact on the impedance of
the trace due to the thruholes capacitance.

Paul S. Denomme
Backplane Design Engineer
Viasystems Technologies Inc.
Richmond, VA 23113
804-226-5355

> -----Original Message-----
> From: Dave Hoover [SMTP:dhoover@mccurdy.com]
> Sent: Monday, July 12, 1999 6:45 PM
> To: 'si-list@silab.eng.sun.com'
> Subject: RE: [SI-LIST] : Via Capacitances ...
>
> Fred,
> In a previous life I built a 50 Ohm Probe Card.
> The customer then wanted another version with the same
> circuit geometry at 75 Ohms. The only difference was to
> modify the dielectric's to achieve the desired Zo. The
> PCB fab lot was built but the Zo off the PCB's was at
> 69 Ohms (Zo). Failure analysis revealed that when the
> plating was drilled away and the signal trace was milled
> (C'Bre'd) down to and tested that the trace really was
> 75 Ohms. The designer increased the clearances in all
> his planes and a new PCB lot was manufactured.
> That lot achieved the 75 Ohms. So on thick PCB's with
> many plane layers do the vias act like a coax?
>
> Dave
> -----Original Message-----
> From: Fred Balistreri [mailto:fred@apsimtech.com]
> Sent: Friday, July 09, 1999 02:10 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Via Capacitances ...
>
>
> Dr. Edward P. Sayre wrote:
> >
> > Folks:
> >
> > It may not be convenient and may stress your personnel or financial
> > assests, but this is why you make SI measurements to confirm your
> results.
> > Almost anybody who has made the measurement knows that vias for whatever
> > reason turn out to be capacitive. If one checks with Dr. Johnson's
> book,
> > you will find that vias are modeled by both capacitors and inductorance.
> > By both measurement and SPICE simulation, NESA has shown this to be
> true.
> > (See papers on our web site.)
> >
> > (The next sentence should be read in the context that I was one of the
> > original students involved in the development of the Method of Moments
> > field simulators and know a lot about old and new simulation software.)
> > There is ample evidence to show that many field simulator derived SPICE
> > models (especially those from 2-D simulators) are often unreliable with
> > respect to the component values but usually have the correct topology.
> > That is to say, if you make a measurement and then adjust the SPICE
> > component values and re-simulating one or twice, you can get
> satisfactory
> > comparisons with the measurements.
> >
> > Otherwise, there is no way to verify the correctness of field solver
> > derived SPICE models for interconnect physical features like vias or
> > connectors.
> >
> > ed sayre
> > ============
> > At 09:50 AM 7/9/99 -0700, you wrote:
> > >Doug
> > >
> > >I modeled a via some time back with ground planes and
> > >clearance holes through it. I had intended to use the capacitance
> > >to make up for an inductance and needed 300 ff.
> > >
> > >I used an OEA field solver Metal and to my amazement there was
> > >hardly any capacitance. I surmised that this was due to the small
> > >area of the ground planes in tha horizontal direction. Since I needed
> > >capacitance I added some big fat ground vias all around the signal
> > >via, and got the 300 ff.
> > >
> > >Also, HP ADS which is the cadillac of RF simulators models vias
> > >as inductor, as does Touchstone before EEsof got swallowed up by
> > >HP.
> > >
> > >Ron
> > >
> > >Douglas McKean wrote:
> > >
> > >> Could someone give rough estimate
> > >> of via capacitance?
> > >>
> > >> I'm thinking the orientation of the traces
> > >> connected to the via have a major impact.
> > >>
> > >> For instance, an .062 board with a via
> > >> from one side to the other, different
> > >> capacitances would be had with the two
> > >> following constructions ...
> > >>
> > >> I. Top Trace
> > >> -------------
> > >> |via
> > >> -------------
> > >> Bottom Trace
> > >>
> > >> II. Top Trace
> > >> -------------
> > >> |via
> > >> -------------
> > >> Bottom Trace
> > >>
> > >> Ideas? Comments?
> > >>
> > >> Regards, Doug McKean
> > >>
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> > >
> > >--
> > >Ronald B. Miller _\\|//_ Signal Integrity Engineer
> > >(408)487-8017 (' 0-0 ') fax(408)487-8017
> > > ==========0000-(_)0000===========
> > >Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA
> 95131
> > >rmiller@brocade.com, rbmiller@sjm.infi.net
> > >
> > >
> > >
> > >
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> > >
> >
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> > | NORTH EAST SYSTEMS ASSOCIATES, INC. |
> > | ------------------------------------- |
> > | "High Performance Engineering & Design" |
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> > | Dr. Ed Sayre e-mail: esayre@nesa.com |
> > | NESA, Inc. http://www.nesa.com/ |
> > | 636 Great Road Tel +1.978.897-8787 |
> > | Stow, MA 01775 USA Fax +1.978.897-5359 |
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>
> I'm not sure what people mean when they say its capacitive or inductive.
> A via consist of capacitance, inductance and resistance. It is true
> that for normal PCB designs a via would have a lower impedance profile
> than a 50-80 ohm PCB trace when subjected to a TDR pulse. Because of
> the sqrt l/c equation one may conclude that the ratio of capacitance
> to inductance is higher on a via than a trace. This may be true in
> most designs but is by no means a rule. The physical dimension of the
> via and the proximity to gnd/pwr planes will determine this ratio.
> As mentioned previously, the size of the cutout in the planes when the
> via passes through them also has a large impact on capacitance. There
> are 2d solvers that do a respectable job of calculating a via model.
> We currently are seeing some designs with microvias. Those type of vias
> tend to have a ratio that may lend them to be "inductive" when compared
> to PCB traces. So I can't believe any of the arguments I've heard so
> far. A measurement is only good for the structure you are measuring.
> If the structure changes one cannot apply the same rules without first
> obtaining more data points. Its always a good sanity check to see if
> the measurement results tend to agree with theory as well. High
> frequency measurements of this type are not the easiest to make.
>
> Best Regards,
> --
> Fred Balistreri
> fred@apsimtech.com
>
> http://www.apsimtech.com
>
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