Re: [SI-LIST] : Idsat variation

Mike Degerstrom (degerstrom.michael@mayo.edu)
Mon, 23 Aug 1999 08:52:34 -0500

Jim,

Thanks for the insight on temperature variation. I did omit the
(1+lambda)*VDS part of the equation intentionally to simplify the
equation. Otherwise your equation matches the one that I have so
maybe we have the same textbook (Gray/Meyer). I simply chose to
rewrite the mosfet equation in the saturation region to make for
easier analysis.

As D.C. Sessions pointed out, my simpler equation was wrong. So
for an n-channel in the saturation region with an equation as:

IDS=IDsat*(VDS/VT-1)^2,

would you have a good idea how much IDsat will vary at a fixed
temperature (say 25C)?

Mike

On Aug 20, 6:49pm, Jim Freeman wrote:
> Subject: Re: [SI-LIST] : Idsat variation
>
> Hi Mike,
> IDS does increase with Vds by the value (1+lambda)*VDS where lambda is
the slope of the ID curve in the saturated region. The increase current is due
to a phenomenon called channel length modulation. In addition to this
> change in current, there are two other temperature effects that have to do
with mobility of carriers in the channel and the doping level in the channel.
Since the mobility is a function lattice scattering, it is inversely
> proportional to temperature and the k factor is directly proportional to the
mobility.
>
> The current equation is IDS = k' w/l((Vgs-Vt)**2)*(1+lambda)*Vds in
saturation.
>
> The linear region of operation is a little simpler and is the final
region of operation when an n-channel device has pulled a node fully to a low.
>
> Mike Degerstrom wrote:
>
> > Jim,
> >
> > Thanks for your reply. I'm no device physicist but I don't
> > think Idsat should be a function of voltage. Certainly voltage
> > variation affects a CMOS buffer drive strength. However
> > I was asking for Idsat for the following equation relating drain current
> > to the gate-to-source voltage for a CMOS device in the ohmic region:
> >
> > ID=IDsat(VGS-VT)^2
> >
> > Also, I haven't been able to find the relationship between Idsat
> > and temperature in my text books.
> >
> > BTW, for anyone else that wants to contribute - please don't
> > supply PROPRIETARY information that you have from foundrys that
> > you work with.
> >
> > Mike
> >
> > > HI Mike,
> > >
> > > You can expect a 4:1 variation over Process,voltage, and temperature
for
> > 3 sigma process models.
> > >
> > > Jim Freeman
> > >
> > >
> > > Mike Degerstrom wrote:
> > >
> > > > Can anyone tell me what reasonable Idsat variations one could
> > > > expect from a typical CMOS line? Could you please qualify your
> > > > answers such as "these are +/- 3 sigma numbers" if at all possible?
> > > >
> > > > Mike
> >
> > --
> > _______________________________________________________________
> > Mike Degerstrom Email: degerstrom.michael@mayo.edu
> > Mayo Clinic
> > 200 1st Street SW
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> > _______________________________________________________________
> >
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>-- End of excerpt from Jim Freeman

-- 
_______________________________________________________________
Mike Degerstrom         Email:    degerstrom.michael@mayo.edu	
Mayo Clinic 
200 1st Street SW 
Gugg. Bldg. RM 1042A                 Phone:    (507) 284-3292
Rochester, MN 55905                    FAX:    (507) 284-9171
WWW:  http://www.mayo.edu/sppdg/sppdg_home_page.html
_______________________________________________________________

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