As far as power delivery is concerned, ferrite beads have low impedance at
DC and low frequency. Charging up decoupling caps at a slow speed is not
degraded. High-frequency surge current will be blocked by the ferrite beads,
but will be provided by the high-frequency decoupling caps placed between
the beads and the VCC pins of the chip. This is exactly what the design goal
is - don't want to see high-frequency current on VCC/GND plane.
When EMI problems are at close to 1GHz, caps are effectively inductors.
Putting more caps down will lower the effective decoupling impedance, but
limited by cost and space (if you can't get caps close to pins, it is a
waste of money).
Again, application need dictates its solution. The app note mentioned is use
on 100MHz motherboard. It has been proved to effectively reduce radiation
and meet SI requirements at the same time. I am not advocating it is a
universal solution for all applications.
-Michael T. Zhang
Platform Architecture Lab (PAL), Intel Corp
From: Ray Anderson [mailto:raymonda@radium.Eng.Sun.COM]
Sent: Friday, March 05, 1999 9:45 AM
Subject: RE: [SI-LIST] : A Question About Power Noise.
Michael Zhang wrote:
> I agree with Han's statement about series inductance and decoupling caps.
> However, a series inductor is still needed even when decoupling caps are
> properly placed.
> High frequency currents take the least inductive path. At the presence of
> decoupling capacitors across VCC/GND, there are two possible paths:
> decoupling caps or through VCC/GND planes. Caps have series inductance
> (ESL), which makes them not as effective above their resonant frequencies.
> Therefore, to prevent high-f current to be sourced from VCC/GND planes
> causing EMI problems, one fix is to have a series inductor - typically a
> ferrite bead - to increase the VCC/GND loop inductance with respect to the
> decoupling cap ESL. This technique is generally applied to VCC, but could
> extended to GND as well. The app note, "CK100 Clock Buffer Preliminary EMI
> Layout Guideline," available at http://developer.intel.com/ial/sdt/, gives
> such an example.
> -Michael T. Zhang
> Platform Architecture Lab (PAL), Intel Corp
> (503) 264-2301
The underlined statement above is correct with respect to the fact
a series inductance will prevent high freq. current from being drawn from
the power planes, but I draw a different conclusion.
A power distribution system (PDS) is usually composed of
at least 4 parts: Voltage Regulator, bulk capacitance, ceramic decaps, and
power planes. Each part is effective over a certain bandwidth. The typical
VR can provide current in response to a delta-I of the load up to a perhaps
10KHz, above that the bulk caps provide a current source that can respond up
to maybe 100KHz or so. Then the ceramic decoupling caps come into play and
are effective up to perhaps a couple hundred MHz. Then the system relies on
the energy stored in the interplane capacitance to respond at higher
By intentionally placing inductance in series with the power planes
and the load you are limiting the ability of the PDS to act as a low
source of power for the load. Granted, the conducted EMI radiation might be
reduced, but then again if the system doesn't perform properly because
introduced a high impedance in the PDS at a critical frequency what have you
gained? Also, I'm not convinced the inductor is a panacea for radiated EMI
I think it is more effective to provide proper decoupling capacitors
on the plane properly placed to achieve a low broadband impedance rather
than introducing inductance to try to mask the EMI effects.
Proper bypassing can provide a good SI environment as well as
a good EMI environment in a system, whereas the addition of series
inductance may be OK from a EMI perspective but is definitely counter-
productive from a SI perspective.
Anyway, that is my humble personal perspective on the topic.
Sun Microsystems Inc.
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