Re: [SI-LIST] : minimizing backplane clock jitter

Dave Underland (dunderland@cyras.com)
Mon, 03 May 1999 08:53:08 -0700

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John,

Good question. I do not have an answer, but one more question. Your
figure below suggests a max length of 8 In.
I believe that worst case is closer to 18 In. Just an observation.

Dave U.

john lipsius wrote:

> All,
>
> I'm requesting recommendations on methods, specific vendors'
> chips, etc., to minimize jitter in backplane clock distribution.
>
> Currently,
> 1. backplane (copper only) distributes 80MHz clock point to point
> using LVDS driver & receiver for each load, from a central point
> that uses a sufficiently low jitter clock generator for Sonet.
> 2. Each receiving board uses the distributed clock (refclk) for a
> Sonet xcvr's refclk input and other loads.
> 3. We're using the Teradyne VHDM connector for the backplane conn.
> 4. sonet xcvr refclk input is LVTTL (Vil=.8v Vih= 2.0v).
>
> Q:
> Without a PLL on the board in (2) to help buffer refclk and remove
> jitter, refclk jitter will likely cause violations in the Sonet
> optical signal
> transmitted and, possibly, higher received-data BER, correct?
> However, any PLL will just pass through in-band jitter to its output
> and to the Sonet xcvr, no? Any suggestions?
>
> Assume all other signal integrity design rules are taken (min. stubs,
> vias, optimum terminations, yada yada).
>
>
> backplane LVDS clk
> |
> |--8in max--> |pcb
> |refclk rcvr-->PLL-->sonetxcvr
>
>
> --
> Thanks,
> John Lipsius
> Member Technical Staff
> Cyras Systems, Inc.
> 46832 Lakeview Blvd.
> Fremont, CA 94538
> 510-623-6631
>

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John,

Good question. I do not have an answer, but one more question. Your figure below suggests a max length of 8 In.
I believe that worst case is closer to 18 In.  Just an observation.

Dave U.

john lipsius wrote:

All,

I'm requesting recommendations on methods, specific vendors'
chips, etc., to minimize jitter in backplane clock distribution.

Currently,
1. backplane (copper only) distributes 80MHz clock point to point
    using LVDS driver & receiver for each load, from a central point
    that uses a sufficiently low jitter clock generator for Sonet.
2. Each receiving board uses the distributed clock (refclk) for a
    Sonet xcvr's refclk input and other loads.
3. We're using the Teradyne VHDM connector for the backplane conn.
4. sonet xcvr refclk input is LVTTL (Vil=.8v   Vih= 2.0v).

Q:
Without a PLL on the board in (2) to help buffer refclk and remove
jitter, refclk jitter will likely cause violations in the Sonet optical signal
transmitted and, possibly, higher received-data BER, correct?
However, any PLL will just pass through in-band jitter to its output
and to the Sonet xcvr, no?  Any suggestions?

Assume all other signal integrity design rules are taken (min. stubs,
vias, optimum terminations, yada yada).
 

backplane LVDS clk
|
|--8in max--> |pcb
              |refclk rcvr-->PLL-->sonetxcvr
 

--
Thanks,
John Lipsius
Member Technical Staff
Cyras Systems, Inc.
46832 Lakeview Blvd.
Fremont, CA 94538
510-623-6631
 

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