Re: [SI-LIST] : low jitter PLL ?

Kassem Abdallah (kabdalla@emc.com)
Thu, 3 Jun 1999 10:25:30 -0400 (EDT)

> From owner-si-list@silab.eng.sun.com Thu Jun 3 00:43 EDT 1999
> Date: Wed, 02 Jun 1999 21:03:34 -0700
> From: john lipsius <jlipsius@cyras.com>
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> To: si-list posting <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : low jitter PLL ?
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>
> All,
>
> Does anyone know of a low-jitter PLL commercially
> available for 78MHz clock buffering/noise-filtering
> application?
>
> For distribution on a pcb.
>
> The intrinsic jitter generated should be in the 20ps RMS range,
> if possible.
>
>
> --
> Thanks,
> John Lipsius
> Member Technical Staff
> Cyras Systems, Inc.
> 46832 Lakeview Blvd.
> Fremont, CA 94538
> 510-623-6631
>
>
>
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>
>
John,

Look at the Motorola Web page for their clock PLL's , Mainly their
MPC9## family (where ## are used for different part numbers). an
example is the MPC952(+- 100ps cycle-2-cycle jitter, up t0 180MHZ
specifications)

Pls Note, the above device was JUST AN EXAMPLE.

Also, I recommend looking at the www.cypress.com they have a variety of
PLL's and Clock drivers.

Thx.

Kassem M. Abdallah
HW Engineer
EMC Corp.

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