You should somehow get allowance for the test load. Some simulators
automatically adjust your timing results for the difference in test load and
actual load. If yours didn't, then I believe you're right - you have a 2.5ns
From: Andrew Phillips [mailto:firstname.lastname@example.org]
Sent: Thursday, May 27, 1999 10:02 AM
Subject: [SI-LIST] : question about timing analysis
Have been doing some IBIS simulations of a circuit to determine
interconnection delays and whether they are small enough to satisfy
timing requirements. The datasheet for the device driving the circuit
states that all timing parameters are quoted as if the driver was
connected to a 50ohm series resistor and a 30pF load.
Now, when I simulate the driver connected to this load it shows that
rise and fall waveforms at the load take 2.5ns to reach threshold
Instead of having this test load I (of course) actually have my specific
circuit. The voltages at the load now take 5ns to settle.
The driver is an address line going to a SDRAM. The datasheet for the
driver says that the address is valid 6ns after a clock.
Here's the question - to determine whether the address will be settled
in time at the SDRAM input is it safe to assume that I can subtract the
2.5ns (for the test load) from the address valid timing spec and instead
add the settling time of my actual circuit (i.e. address valid after
clock = 6ns - 2.5ns + 5ns = 8.5ns) ??
Thanks for any help,
Supercomputing Systems AG
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