Re: [SI-LIST] : Best type of models, edge rates & load

Mark Nass (markn@rccorp.com)
Tue, 20 Jul 1999 15:52:05 +0100

No this was no surprise.
this is what I do. I also include the power and ground package parasitics
when I generate the data. I don't use the 10% point for timing though, I use
something more like 1/2 VDD. I have been using the 50 ohm pullup & pulldown
for the waveform generation, but for Tco values I have been using 500 ohm
to 1/2 VDD. When the Tco number and flightime numbers are added up this
seems to correlate with the numbers in the lab pretty well. The only part that
doesn't is the Tco value by itself, and this seems to bother some people. The
Tco value into a 500 ohm to 1/2 VDD is much quicker than a loaded transmission
line in the lab.

Mark

At 02:32 PM 7/20/99 -0700, you wrote:
>Mark Nass wrote:
>>
>> There has been some discussion recently about parameters of parts
>> specified into 40pf caps and accuracy of models. I generate this type
>> of data for our devices for our own use and our customers. So I am
>> curious as to what people think would be the optimal way to generate
>> Tco, Tsu, jitter parameters and IBIS models so that they would be confident
>> they were getting exactly what they needed for signal integrity and timing
>> analysis. Any feedback?
>
>If you had to pick just one load, it would be 50 ohms. Notice I didn't
>write "50 ohms and 30 pf" or anything like it. To get the best sims we
>need the high-frequency content of output waveforms, and artificially
>filtering it out by adding a lowpass is not exactly helpful.
>
>Of course, we need both the turnon and turnoff responses for both
>the pullup and pulldown paths, so that's four tables (rising into
>50 ohm pullup, falling into 50 ohm pulldown, rising into 50 ohm pulldown,
>and falling into 50-ohm pullup.
>
>Output timing should be to the 10% (initial) point of the edge. That's
>easy to plug in as Vmeas so that the timing numbers add up, and also
>easy enough to measure on a tester so that you're actually testing to
>the critical design parameter.
>
>No lumped caps anywhere (was this a surprise?)
>
>--
>D. C. Sessions
>dc.sessions@vlsi.com
>
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