Re: Q:Via Capacitance....Re: [SI-LIST] : Pass-through vias as BGA lands

Chandrakant Hemraj Sakharwade (sakh@cadence.com)
Wed, 10 Mar 1999 09:03:55 +0531 (IST)

Nope. D1 is the annular ring dia and D2 is the clearance hole dia
(on ground plane). Via dia itself is not coming into picture.

-Sakh
> From owner-si-list@silab.eng.sun.com Tue Mar 9 20:32 IST 1999
> Date: Tue, 9 Mar 1999 09:24:41 -0500
> From: Laurence Michaels <lmichael@techmail.gdc.com>
> X-Mailer: Mozilla 4.5 [en] (X11; U; SunOS 5.5.1 sun4u)
> X-Accept-Language: en, de, es, ru
> MIME-Version: 1.0
> To: Chandrakant Hemraj Sakharwade <sakh>, SI-List <si-list@silab.eng.sun.com>
> Subject: Re: Q:Via Capacitance....Re: [SI-LIST] : Pass-through vias as BGA lands
> (?)
> Content-Transfer-Encoding: 7bit
> Sender: owner-si-list@silab.eng.sun.com
>
> I'm assuming that D2 = annular ring diameter,
> D1 = drill size, and T = Thickness.
>
> Is that correct?
> -- Laurence
>
> Which physical characteristChandrakant Hemraj Sakharwade wrote:
> >
> > Daniel,
> >
> > The value of ~0.53 pF as given in "High-Speed Digital Design"
> > is for a 16 mil via with 28 mil annular ring and 50 mil clearance
> > hole in ground plane (for a 63 mil PCB thickness.)
> >
> > One can reestimate the capaciatance for other geometries
> > (C = 1.41*er*T*D1/(D2-D1)).
> >
> > Microstrip with following geometry has 2.6 pF /inch
> > (Width = 8 mil, height above ground plane = 6 mil,
> > thickness = 2.37 mil, er = 4.5)
> >
> > Hope this helps.
> >
> > -Sakh
> >
> > Cadence Design Systems
> >
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
>
>

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****