Just spoke with my colleague Larry smith about your question
and the concensus is that it is a BAD idea to run traces from
the capacitor to the chip and then connect the composite
mess to the planes via vias .
Why?? Loop area. The loop area of the current path that
describes the circuit from plane 1 up through a via, through
a trace, through a capacitor, back through another trace and
thence to the other plane is much larger than the loop area
from a plane, through a via, through a cap and then to the
Why do we care about loop area? Because the bigger the loop,
the more lines of magnetic flux and hence the higher the inductance.
This translates to a lower SRF among other things. These other
things include making the Q of the bypass higher and hence of
lower bandwidth. This requires the use of more capacitors to
achieve the same bypass effectiveness since our goal is
to create a broadband low impedance for the power distribution
To supplement all the buzzwords, Larry had empirical experience
in that he tried it wrong way once upon a time and swears
he will never do it again..
Run your chip power pins directly to the planes. Run your
decoupling caps directly to the planes (while minimizing the
current loop area and via length).
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