Re: [SI-LIST] : METASTABILITY IN FLIP FLOPS

Howard Johnson (howiej@sigcon.com)
Fri, 16 Jul 1999 09:05:04 -0700

Dear Shayle et. al.,

Here's what I have observed about metastability.

In my experience, I observe that the output of
modern buffered flip-flops tends NOT to oscillate
during the metastable resolution period. I have
measured this behavior on an (admittedly small)
sample of 7400, 74F, and 74HC type SSI flip-flops.

My model for the internal workings of a flip-flop
looks like this:
(A) An internal comparator with a threshold Vc
(B) A positive feedback network around the comparator that
keeps it latched in its present state
(C) A sampling circuit that samples the "D" input and
jams in a signal into the comparator, overwhelming the
feedback and causing it to switch rapidly to the
desired state
(D) A buffer amplifier connected to the output of
the internal comparator, with a threshold Vb

Normally, when the "D" input is sampled, if it conforms
to the setup and hold rules, it should be at a valid
HI or LO level. The sampling circuit (C) will then jam
a full-sized signal into the comparator, causing a
"large-signal response". That is, the comparator
whams to one side or the other right away. The buffer
then responds and you have your output. Under these conditions
the clock-to-Q time is always predictable (and should
meet the published specifications for the part).

If the input is changing within the setup and hold window,
if it is changing just at the moment the sampling
circuit looks at it, an intermediate voltage may be
impressed upon the comparator. This causes an
intermediate response at the output of the comparator.
The positive feedback network then causes a violent
exponential buildup of feedback which forces the comparator
to quickly go one way, or the other.

Modern parts
are pretty well-damped internally, so I would be
very suprised to see osciallation. What I expect to
see at the comparator output is first an intial output
level related to the difference between the sampled
input level and Vc, times the comparator gain).

If the initial output is even the tiniest bit more
positive than Vc, the feedback will cause a wildly unstable
exponential buildup in the positive direction, ending
with the output slammed into Vcc, above which it
cannot go.

If the initial output is even the tiniest bit less
positive than Vc, the feedback will cause a wildly unstable
exponential buildup in the negative direction, ending
with the output slammed into ground, below which it
cannot go.

In either case, after a suitable number of comparator
amplifier time-constants, the circuit comes to rest.
The number of time constants required depends on
how closely the initial sampled signal approaches Vc.

[By the way, if you assume the comparator response
is exponential, and you assume the sampled waveform
has a linear slope with random time of arrival, you
can show that the distribution of metastable resolution
times should be inverse-exponential, that is, the
probability of observing a resolution time greater than
T should decrease exponentially with T. Observations
confirm this rule, which is the evidence used to
suggest that this model is correct.]

In a buffered part, YOU DON'T SEE THE EXPONENTIAL
ACTIVITY because the buffer squares it up. At the
output of the buffer, depending on the relation
between Vc and Vb, you tend to either get one of
several effects:
(1) The output does the right thing.
(2) The output does nothing at first, then later pops the other way.
(3) The output goes the wrong way at first, then later pops back.

I'll work out one case for you. Suppose the system
begins with the output LO. Let Vcc=3.3V, Vc=1.5V, and Vb=1.4V.
Please don't read anything into my choice of numbers, it's
just an example.

Let the initial sampled voltage be 1.499V. This is less than Vc,
so we know that eventually the system will end in the LO
state. What happens initially, however, is that the
comparator output jumps to a value near Vc, then begins
its descent towards ground. The buffer, because its threshold
happens to be a little below Vc, initially responds HI.
Later, after the comparator output sinks below Vb, the
output changes its mind and snaps LO.

On old unbuffered CMOS logic, or logic built from electron tubes,
you can sometimes see the exponential response directly at the
output. On modern logic with a buffered output stage, you
just see the late transition. This late transition causes
a problem for the succeeding logic stages only if it happens
to change during the setup and hold window for the next stage.

In a state machine, the spread between the required setup and
hold times (as defined at the output of our possibly-metastable
sampling flip-flop) is pretty wide. If the width of this interval
is appreciable compared to one internal comparator time-constant
then the probability of getting a late transition SOMEWHERE in
that window is pretty much the same as the probability of receiving
a late transition ANYWHERE after the setup requirement. In state
machine work, we generally just compute the probability of a
metastable resolution time GREATER than T.

Inside the metastable synchronizer itself, things work a little
differently. The metastable resolution delay at the output of
the first flip-flop causes a problem ONLY if it hits RIGHT ON TOP
of the actual sampling moment for the second flip-flop. Since
this second window is extremely narrow, our statistics benefit
not only from the additional total resolution time made
available by the circuit, but also from the relation of the
effective metastable sampling window width to the comparator time
constant. I believe this effect accounts for the superiority
of the two-stage (or three-stage) sampler over a single-stage
sampler with a slower clock.

I think John Wakerly covers a lot of good points about
metastability in his book, "Digital Design Principles and
Practices", Prentice-Hall, 1990 ISBN 0-13-212838-1. He
has a nice "ball and hill" description that I find
very helpful.

I'd be very interested to hear anyone else's experience on
this matter.

Best regards,
Dr. Howard Johnson

P.S. - the circuit I use to investigate metastability is
given on p. 121 of my book, "High-Speed Digital Design".
It hammers a flip flop with worst-case input timing violations
at a rate of 1 MHz. It incorporates a feedback circuit that
keeps the input violations centered (subject to noise limitations)
within a few picoseconds of the actual sampling moment. With
this circiut I can easily observe metastable resolution times
well in excess of 5 times the normal clk-to-Q transition time,
and can demonstrate the exponential-decreasing-probability
law.

At 08:58 AM 7/15/99 -0700, you wrote:
>Dr. Johnson,
>
>Are you saying that using two flip flops in series with a clock whose
>frequency is too fast to include the extra time allotted for meta state
>resolution works successfully since the probability of the output of the
>first flip flop changing during the vulnerable input time of the second
>flip flop is very low?
>
>That's an interesting idea which, if true, can enable the the clock
>frequency to stay optimally high.
>
>I had thought that the meta state of the first flip flop was an unsafe time
>to clock into the second flip flop. But you say there aren't any
>oscillations and that it will be a valid high or low during the meta state,
>possibly changing again at the end of its meta state when it makes its
>final decision.
>
>Shayle
>
>
>*************************************************************
>Shayle I. Hirschman, Senior Engineer
>Managing Director
>Digital Design Solutions
>http://www.digital-designs.com
>shayle@mho.net
>Phone 901/759-1802 Fax 901/759-2324
>
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_________________________________________________
Dr. Howard Johnson, Signal Consulting, Inc.
tel 425.556.0800 fax 425.881.6149 email howiej@sigcon.com

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