[SI-LIST] : Slow falling edge of a signal.

johnlin@ccmail.arima.com.tw
Wed, 10 Mar 1999 08:58:33 +0800

Dear all SI gurus,

One question.

For a CMOS chip, what will be effects for a slow falling edge ( 2ns from 1.5V to
0.8V) of an input?
Will the chip work abnormally?

Based on its' timing specification , the setup time measurement is to measure
1.5V on a clock rising edge to 1.5V on the falling edge of the signal.

Shall it be 1.5V on the clock rising edge to 0.8V of the falling edge of signal
for the setup time measurement?
That is because 0.8Volt is a guarantied low state.

Any comments from you are appreciated.

Thanks,

John Lin
CAE Engineer @ Arima
Johnlin@ccmail.arima.com.tw

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