[SI-LIST] : PC100 SODIMM DRAM DQ Net Simulations

[email protected]
Fri, 21 May 1999 10:53:23 -0400

From: Gregory N Heiler


I am setting up a board simulation that contains several SODIMM Modules.
Depending on the build, anywhere from 1 to 4 of these modules may be
loaded. I've modelled the SODIMM Module as an EDB with generic interconnect
statements per the Intel PC100 SODIMM Specification. I've coded in the DQ
10 ohm source termination resistors as zero length interconnect of
resistance 10 ohms. For SDRAM Models, I am using an Hitachi Model (
HM5216165TT10) modified for x16 compliance.

The DQ nets consists of a SN74LVCHR162245ADL Transceiver and the
corresponding DQ Pins on the SODIMM's. Since the SODIMM's are 64 bit, and
32 bit are being accessed, the net connects to 2 DQ Pins on each SODIMM
(i.e. DQ(2) & DQ(34)). I'll be needing to analyze the conditions where from
1-4 SODIMM's are loaded using the ICX IS Tool. The initial simulations are
being run with a Zo of 50 ohms on the board and the write wave forms show
major problems with reflections. I'll be exploring topology, termination
and impedance options in an attempt to see if signal integrity can be

I believe this is a common problem and was hoping those who have tackled
this problem before would be willing to share what has worked for them. All
comments and recommendations would be appreciated.

Regards and Thank-You;

Greg Heiler

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