RE: [SI-LIST] : even-odd mode influence

Douglas McKean (dmckean@corp.auspex.com)
Fri, 16 Jul 1999 13:24:08 -0700

Nanosecond edge rates (10^-9) requires ~ 500 MHz BW.
1/2 nanosecond edge rate requires ~ 1 GHz BW.
... and so on.

Now I ask - take a trace, any trace no matter what it
is and reduce it to it's lumped or non-lumped parameters
of resistance, capacitance and inductance. Look at it
as a "circuit" now and ask yourself if this "circuit"
can actually support a flat BW out to ... whatever it is.
Since board houses measure controlled impedances with
only 1 MHz unless specifically told otherwise,
my bet is no.

A designer may want to argue by way of Shannon's
Theorem that data rates with S/N ratios on the
order of 30 dB or more need only 50 MHz or so BW.
But, edge rates can easily swamp that out very
quickly in terms of orders of magnitude. And with
it, I submit, all of the above also.

Sorry for the lengthy discussion but my point is ...

Put that one circuit in parallel with others and the
odd versus even impedance effects makes this situation
all the worse by changing phase and group velocities.
Thus one ends up with smeared or "slurry" edges. That
in turn *could* effect setups, prop delay, metastability,
and ultimately latency. I'm of course painting a
really worst case scenario.

And as you say, Weber, with the onset of faster edge
rates and fine pitch constructions, we are stuck.
And all we've got so far is trade offs.

Regards, Doug McKean

At 10:37 AM 7/16/99 +0800, Weber Chuang wrote:
>Hey! Hey! Doug, you really got my point, though xtalk is one of my concern
>since the swing is now smaller(1.5 Volt), while the edge rate seems to stay
>the same or even get faster, however, what bothers me most is that when we
>are designing PCB for PC133 , there are so many signals in a bus such that
>we cannot avoid to put them in adjacent to each other(not widely separated),
>here comes the problem, the difference of about 30 %(even higher if the
>trace width:cleance is 1:1 or 1:1.5 and stackup not well arranged and 7
>conductor considered) in impedance between even and odd mode will make the
>termination scheme fail and the estimation of ISI jittering become very
>difficult, besides, it will also be data pattern dependent. If I cannot
>analyze(simulate) the ISI jittering correctly, I cannot do static timing
>analysis correctly, that resides my problem. Thanks in advance for any
>comment and discussions.
>
> Best Regards
>
> Weber Chuang(ChingFu Chuang)

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