Re: [SI-LIST] : Different board vendors different impedances

Ron Miller (rmiller@Brocade.COM)
Thu, 25 Mar 1999 10:12:49 -0800

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Kim

I am appaled by this vendors remarks but not surprised.

We engineers design the boards and if some fab houses do not want to build them
as directed, or maintain the tolerances required then we will find someone who will.

The fab houses have no way of knowing that a pad size is designed to provide a
capacitance that is optimized and simulated to make the entire circuit work as
desired. They do not make differential impedance measurements for differential
lines.

Basically, what it boils down to is that they have been getting away with
adjusting their processes and even the artwork to get the impedances that are specified
because they have not been keeping their materials properties dimensions and
post process trace widths to the fab drawing requirements.

It is time for that to change. I for one will not let the PCB fab house design the board
for me.

Ron Miller

Kim Flint wrote:

> At the PCB West conference yesterday, during the course on Materials for
> High Speed Design (which was quite interesting, I wasn't familiar with
> much
> other than FR-4, but that's another topic....) a fellow in the audience
> happened to be from a major fab house and made some rather interesting
> comments that seem to pertain to your questions.
>
> One was that FR-4 material is made by a variety of vendors, and it is
> not
> all the same. A fab house will be taking those differences into account
> for
> their controlled impedance calculations, depending on the material
> vendor
> they use. This could account for differences, even if processes are
> supposedly equivalent otherwise. (In any case, the dielectric constant
> for
> FR-4 is not very stable and could be a signigicant source of error.)
>
> He also said about the same thing Katie said below, that different fab
> houses tweak their calculations according to empirical data from their
> particular process.
>
> Most interestingly, he said they've lately had a lot of trouble with
> engineers possibly knowing a little too much for their own good (or not
> enough :-) and trying to achieve controlled impedance just through
> specifying trace widths, copper weight and stackup dimensions. Since the
> real world of PCB fabrication is not that ideal, and all fab houses are
> not
> equal, this often results in completely wrong results on the board. And
> the
> fab house can't do anything about it since they don't really have enough
> info to know how to compensate their process to meet your requirement.
> His
> request to engineers was to include, in addition to stackup, trace
> width,
> etc., the impedance you are targeting, the calculations you used to
> determine that, and any assumptions you might have made. (i.e., Er=4.3.)
> This info should be *on the fab drawing*, as that is the thing that will
> actually get looked at during fabrication. With this data, the fab house
> should be able to compensate appropriately for their process, and
> therefore
> they might be able to do a better job of getting you what you want.
>
> good luck...
>
> kim
>
> At 01:51 PM 3/24/99 -0500, Laurence Michaels wrote:
> >Katie Rothstein wrote:
> >>
> >> Laurence,
> >> Just a quick thought about your question. Different board vendors have
> >> different processing capabilities (line width, total board thickness, board
> >> size, etc.) This could be why some board shops can meet your required
> >> impedances and some cannot. I'm not sure exactly what you are asking
> about the
> >> different calculations, but many board houses have impedance calculation
> tools
> >> that take empiricle data to help make corrections for their own processes.
> >> -Katie
> >
> >It sometimes seems that, even with 'equivalent' processes, allowing the
> >same board thickness, size, line width, and layer stackup, board vendors
> >will come up with different values for trace impedance, generally
> >requiring them to tweak the board stackup. Since we sometimes like to
> >use different board vendors, even on the same board, it would be nice to
> >be able to specify FR4 and copper, and use only one layer stackup,
> >instead of having to keep track of which vendors require which different
> >dielectric heights. It would be even better to come up with a
> >theoretical calculation that works in practice, since some people seem
> >to think that anything should be able to be calculated without having to
> >add tweak factors for different vendors. I'm beginning to realize that
> >this is not the case.
> >
> >What I'd really like is to come up with a set of layer stackups, perhaps
> >including different stack heights for different vendors, for a few
> >different controlled impedances and numbers of layers. Doesn't seem too
> >likely, as even including the true dielectric constant for the specific
> >vendor's material in the calculation doesn't always come out within 10%
> >of the measured impedance. Plus I'd rather only have one layer stackup
> >(including diel. heights) per board, regardless of vendor. Wishful
> >thinking...
> >
> >I'd also like a less expensive way to measure trace impedance than a
> >TDR, so that we can check the board vendor's claims ourselves. Any
> >ideas here?
> >
> >-- Laurence
> >
> >**** To unsubscribe from si-list: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list, for more help, put HELP. si-list archives are accessible at
> http://www.qsl.net/wb6tpu/si-list ****
> >
> >
> >
> ________________________________________________________
> Kim Flint, MTS 408-752-9284
> ATI Research kflint@atitech.com
> http://www.atitech.com
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

--
Ronald B. Miller  _\\|//_  Signal Integrity Engineer
(408)487-8017    (' 0-0 ') fax(408)487-8017
     ==========0000-(_)0000===========
Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA  95131
rmiller@brocade.com,  rbmiller@sjm.infi.net

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> Kim

I am appaled by this vendors remarks but not surprised.

We engineers design the boards and if some fab houses do not want to build them
as directed, or maintain the tolerances required then we will find someone who will.

The fab houses have no way of knowing that a pad size is designed to provide a
capacitance that is optimized and simulated to make the entire circuit work as
desired.  They do not make differential impedance measurements for differential
lines.

Basically, what it boils down to is that they have been getting away with
adjusting their processes and even the artwork to get the impedances that are specified
because they have not been keeping their materials properties dimensions and
post process trace widths to  the fab drawing requirements.

It is time for that to change.  I for one will not let the PCB fab house design the board
for me.

Ron Miller

Kim Flint wrote:

At the PCB West conference yesterday, during the course on Materials for
High Speed Design (which was quite interesting, I wasn't familiar with
much
other than FR-4, but that's another topic....)  a fellow in the audience
happened to be from a major fab house and made some rather interesting
comments that seem to pertain to your questions.

One was that FR-4 material is made by a variety of vendors, and it is
not
all the same. A fab house will be taking those differences into account
for
their controlled impedance calculations, depending on the material
vendor
they use. This could account for differences, even if processes are
supposedly equivalent otherwise. (In any case, the dielectric constant
for
FR-4 is not very stable and could be a signigicant source of error.)

He also said about the same thing Katie said below, that different fab
houses tweak their calculations according to empirical data from their
particular process.

Most interestingly, he said they've lately had a lot of trouble with
engineers possibly knowing a little too much for their own good (or not
enough :-) and trying to achieve controlled impedance just through
specifying trace widths, copper weight and stackup dimensions. Since the
real world of PCB fabrication is not that ideal, and all fab houses are
not
equal, this often results in completely wrong results on the board. And
the
fab house can't do anything about it since they don't really have enough
info to know how to compensate their process to meet your requirement.
His
request to engineers was to include, in addition to stackup, trace
width,
etc., the impedance you are targeting, the calculations you used to
determine that, and any assumptions you might have made. (i.e., Er=4.3.)
This info should be *on the fab drawing*, as that is the thing that will
actually get looked at during fabrication. With this data, the fab house
should be able to compensate appropriately for their process, and
therefore
they might be able to do a better job of getting you what you want.

good luck...

kim

At 01:51 PM 3/24/99 -0500, Laurence Michaels wrote:
>Katie Rothstein wrote:
>>
>> Laurence,
>>      Just a quick thought about your question.  Different board vendors have
>> different processing capabilities (line width, total board thickness, board
>> size, etc.)  This could be why some board shops can meet your required
>> impedances and some cannot.   I'm not sure exactly what you are asking
about the
>> different calculations, but many board houses have impedance calculation
tools
>> that take empiricle data to help make corrections for their own processes.
>> -Katie
>
>It sometimes seems that, even with 'equivalent' processes, allowing the
>same board thickness, size, line width, and layer stackup, board vendors
>will come up with different values for trace impedance, generally
>requiring them to tweak the board stackup.  Since we sometimes like to
>use different board vendors, even on the same board, it would be nice to
>be able to specify FR4 and copper, and use only one layer stackup,
>instead of having to keep track of which vendors require which different
>dielectric heights.  It would be even better to come up with a
>theoretical calculation that works in practice, since some people seem
>to think that anything should be able to be calculated without having to
>add tweak factors for different vendors.  I'm beginning to realize that
>this is not the case.
>
>What I'd really like is to come up with a set of layer stackups, perhaps
>including different stack heights for different vendors, for a few
>different controlled impedances and numbers of layers.  Doesn't seem too
>likely, as even including the true dielectric constant for the specific
>vendor's material in the calculation doesn't always come out within 10%
>of the measured impedance.  Plus I'd rather only have one layer stackup
>(including diel. heights) per board, regardless of vendor.  Wishful
>thinking...
>
>I'd also like a less expensive way to measure trace impedance than a
>TDR, so that we can check the board vendor's claims ourselves.  Any
>ideas here?
>
>-- Laurence
>
>**** To unsubscribe from si-list: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP.  si-list archives are accessible at
http://www.qsl.net/wb6tpu/si-list ****
>
>
>
________________________________________________________
Kim Flint, MTS                  408-752-9284
ATI Research                    kflint@atitech.com
http://www.atitech.com

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.  si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

-- 
Ronald B. Miller  _\\|//_  Signal Integrity Engineer
(408)487-8017    (' 0-0 ') fax(408)487-8017                 
     ==========0000-(_)0000=========== 
Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA  95131
rmiller@brocade.com,  rbmiller@sjm.infi.net
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