> Depending on application need, the effectiveness/consequence of using a
> series inductive element can vary dramatically. Signal radiates not only at
> it fundamental frequencies, but more profoundly at it harmonic frequency (if
> it is not a pure sinusoidal signal). So it is desirable for the series
> inductive element to have high impedance at the problem frequency, but low
> impedance at the signal (fundamental) frequency. This is why ferrite bead, a
> frequency selective device, is widely used in this technique. Practically,
> signal edge rate will be slowed down a bit. Then it is a trade-off design
> between meeting SI and EMI requirements.
Agreed, from the perspective of the chip looking out towards
the rest of the system, a series L or ferrite component can
provide an effect low pass filter to restrict the noise
from being conducted onto the planes. But remember the
filtering effect is bidirectional, so the isolation you've
achieved to prevent noise from escaping is also isolating
your chip from the benefits of the power planes.
> As far as power delivery is concerned, ferrite beads have low impedance at
> DC and low frequency. Charging up decoupling caps at a slow speed is not
> degraded. High-frequency surge current will be blocked by the ferrite beads,
> but will be provided by the high-frequency decoupling caps placed between
> the beads and the VCC pins of the chip. This is exactly what the design goal
> is - don't want to see high-frequency current on VCC/GND plane.
But when we are dealing with systems that have clock rates
of several hundred MHz or more where is the reservoir of current
that will required at the clock rate and perhaps at multiple
Fourier components of the clocks? Decoupling capacitors, as you have
noted become less effectual above resonance where they begin
to look more like inductors than capacitors. The "high quality"
capacitance provided by the power planes is the source of these
very high frequency current demands. The amount of effective
capacitance that is available at a particular circuit node is
limited by the planes' spreading inductance but is still effective
at much higher frequencies than can be provided for by discrete
capacitors. Discrete decoupling caps just run out of performance at
very high frequencies. It isn't just the ESL of the cap that we need
to be concerned with, but with the mounted inductance which is
comprised of partials contributed to by the pads, vias, spreading
inductance, and probably most important the size of the current loop.
By providing closely spaced power/ground planes and using
multiple parallel planes if necessary you can achieve
very good EMI and SI performance at very high frequencies.
> When EMI problems are at close to 1GHz, caps are effectively inductors.
> Putting more caps down will lower the effective decoupling impedance, but
> limited by cost and space (if you can't get caps close to pins, it is a
> waste of money).
And circuit board planes can be cheaper than caps.... Caps
that need to be effective at very high frequencies need to be close
to the part they are decoupling. Caps that are intended to decouple
lower frequencies can be placed proportionately farther away and still
be effective. At 1GHz the most effective "cap" is a power plane.
> Again, application need dictates its solution. The app note mentioned is use
> on 100MHz motherboard. It has been proved to effectively reduce radiation
> and meet SI requirements at the same time. I am not advocating it is a
> universal solution for all applications.
Agreed, there is no one best solution. In some cases the
use of series inductors may be a good solution, however
I think those times are probably a minority of the cases.
We've found that proper attention to decoupling over a
wide bandwidth (picking the right decoupling values, number
of caps, cap dielectric, placement of caps, and power distribution
plane geometry) can provide a very effective broadband
solution for both SI and EMI performance in most all of the
cases that our group has analyzed.
> -Michael T. Zhang
> Platform Architecture Lab (PAL), Intel Corp
> (503) 264-2301
Thanks for your inciteful comments and suggestions. This is
a very important topic for the SI engineer today and I believe
you will be seeing more and more published on the topic. It
can be a complex topic and one needs the proper tools to deal with
power distribution management in todays high performance designs.
Open discussions like this one point out many of the important
areas that need to be dealt with. It is good for opposing points
of view to be discussed in a forum like this.
Sun Microsystems Inc.
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