Regards, M. Chan
Email: Michael.Chan@COMPAQ.com
-----Original Message-----
From: ajmani@us.ibm.com [mailto:ajmani@us.ibm.com]
Sent: Monday, May 17, 1999 4:06 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Decoupling caps and power plane effects
I am trying to run a similar simulation but in a different way, using IBM's
internal PEEC based simulator. Here, I am modeling every ASIC on the board
as a
potential noise source. Bypass capacitors are placed around the ASIC, as
would
be done in the actual board, and are modeled with series inductance and
resistance. The simulator injects broadband noise voltage at every source
location (all noise sources are in-phase), and simulations are done in
frequency
domain. The simulator results show the noise currents in power/ground
planes at
different frequencies, which provide the indication of the effectiveness of
capacitor at that location in suppressing the noise.
Regards, Ravinder
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest. ....
Mark Twain
**** To unsubscribe from si-list: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP. si-list archives are accessible at
http://www.qsl.net/wb6tpu/si-list ****
**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****