RE: [SI-LIST] : Decoupling caps and power plane effects

Chan, Michael ([email protected])
Mon, 17 May 1999 17:17:59 -0500

I use the Pacific Numerix tool which is also a PEEC based simulator to
model the power and ground structure and place capacitors( non-ideal models
) at the appropriate
locations in the circuit simulator to generate the power and ground noise
with very good
result. However, the modeling time and circuit simulation time is very long.

Regards, M. Chan
Email: [email protected]

-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Monday, May 17, 1999 4:06 PM
To: [email protected]
Subject: Re: [SI-LIST] : Decoupling caps and power plane effects

I am trying to run a similar simulation but in a different way, using IBM's
internal PEEC based simulator. Here, I am modeling every ASIC on the board
as a
potential noise source. Bypass capacitors are placed around the ASIC, as
would
be done in the actual board, and are modeled with series inductance and
resistance. The simulator injects broadband noise voltage at every source
location (all noise sources are in-phase), and simulations are done in
frequency
domain. The simulator results show the noise currents in power/ground
planes at
different frequencies, which provide the indication of the effectiveness of
capacitor at that location in suppressing the noise.

Regards, Ravinder
Email: [email protected]
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