RE: [SI-LIST] : How to decouple POWER/GND , heavy current backpla

Heyfitch, Vadim (vadim.heyfitch@intel.com)
Mon, 27 Sep 1999 18:18:25 -0700

Hello Shengli,

first question that comes to my mind is whether 8A/daughter card is a peak
current or an average current. Is this a chip with some 200 GTL (or some
kind of current mode) drivers?

Second, realize that decoupling caps are used to fight transients - i.e
di/dt - and not the current (whether large or small). There are several
levels of hierarchy of decoupling caps: VRM (i.e. voltage regulators) have
some internal decoupling capacitance that can respond to slowly varying
current; bulk capacitors - next level of the decoupling hierarchy - help to
sustain the voltage between the power and ground planes; bypass decoupling
caps - yet another level of the decoupling hierarchy - are placed very close
to the component, and help to sustain the voltage differential between the
power and ground pins of the chip. The latter is effective for the time
scale of 1 to several clock cycles, and usually don't help much with the
fast rising/falling edges. Next level is the pwr/gnd planes around the
component: their "sandwich" provides some capacitance with very low ESL. In
addition, there are possibly on-die decoupling capacitance (from a few to a
few hundred pF per driver) that provides current for high-to-low and
low-to-high transitions. The on-die capacitance is actually the only one
that can be efficient for <1ns rise/fall times.

This while decoupling scheme is meant to keep the voltage rails at the
driver from collapsing. It is impossible to completely avoid some rail
collapsing. A good decoupling scheme can reduce the effect quite
substantially.

Going back to your original concern, you need to estimate di/dt per
component on the daughter card assuming the worst switching pattern ("max
number of drivers switching simultaneously" X "max di/dt of a single
driver").

As to your concern about the 32 Amps, it's more of a thermal issue. Tackle
it with good heat sinks. Also, not all 4 cards are driving simultaneously
(even if a bi-directional signaling is used - which I doubt.)

Good luck with your project.

Vadim

-----Original Message-----
From: liusl [mailto:liusl@ustc.edu.cn]
Sent: Friday, September 24, 1999 10:58 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : How to decouple POWER/GND , heavy current backplane

Dear friends,

My backplane will run signals whose frequency ranges from
62.5MHz to 625MHz, and 4 daughter cards inserted each will
consumes 8A current of 3.3V. A whole PCB plane layer with 2oz Cu
will be used to provide this large current to each daughter
cards, that is the total current on backplane will be 4*8A
=32A, which is so large, I don't know how large and how many
Capacitances should be used on backplane to do decoupling.
Anyone can explain that to me?
thanks a lot.
----------------------------- Shengli Liu, Postdoc
_/_/_/_/ _/_/_/_/ _/ Fast Electronics Laboratory
_/ _/ _/ Department of Modern Physics
_/_/_/ _/_/_/ _/ University of Science & Technology
_/ _/ _/ of China,
_/ _/_/_/_/ _/_/_/_/ Heifei, Anhui, P.R.China, 230027
Phone: 0551-3603154 (o)
Fast Electronics Laboratory http://www.felab.ustc.edu.cn
-----------------------------

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