RE: [SI-LIST] : Signal Polarities

Volk, Andrew M (andrew.m.volk@intel.com)
Thu, 22 Apr 1999 11:01:03 -0700

I disagree if the VIL/VIH are not set symmetrically in the center of the
output voltage swing. Take TTL or even LVTTL levels. The low level is 0.8
against a 1.65 center. Assuming the active level is used less often, you
gain noise margin for the inactive level. Also, drive strength are not
equal between N and P, usually favoring the pull-down. Another asymmetry to
consider for timing edges and slew rates. If you are defining your own
private interface with levels slew rates, then there is little difference.
But when making signal activity level choices for existing signaling
protocols, you may want to look at the relative noise margins.

Andrew Volk
Intel Corp.

-----Original Message-----
From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
Sent: Thursday, April 22, 1999 8:39 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Signal Polarities

Kassem Abdallah wrote:
>
> Hi All,
>
> I wonder if someone can briefly illustrate the pros and cons of using
> Active low signals versus Active High signals.
> - Form both views: a chip design and a board level design
> - From the Drivers technology selection.
> - From a Connection view:
> (a) in case of a piont to point connection.
> (b) multi-node connection.

Since you need to be able to transition in both directions,
there is no difference whatsoever.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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