The plane capacitance is fairly simple to estimate based on the
dielectric constant of the board and the plane to plane spacing. If
however you want time domain voltage droop simulation, you may require a
model of the plane that takes into account the distributive nature of the
plane. You may or may not be permitted to use a lumped model of the plane.
A lumped model of the plane would only be valid in the instance where the
rise time of the current discharging the plane is long relative to the time
it takes a signal to propagate the dimensions of the board. Only then
could you possibly use a lumped model. In that case, the board capacitance
would be negligible compared with most commonly used bypass strategies.
The fact that you site the planes being the first to respond let's me
infer that you are talking about a system where the rise times are short
enough for the system to "see" the difference between the planes
distributed capacitance and a bypass caps lumped capacitance. In this case
you should not expect to use a single lumped model for the plane. You
could use a mesh of lumped equivalent capacitive elements connected
together to form an approximation of the plane's distributive capabilities
in much the same way as one can approximate a transmission line with a
series of lumped elements. In reality a power/ground plane is nothing more
than a fat transmission line and can be dealt with that way to predict all
of the plane's interesting properties such as time domain discharge and
finite plane impedance resonances etc.
Neil Yosinski
Engineer/Scientist
Hewlett Packard CO
Network Systems Test Division
______________________________ Reply Separator _________________________________
Subject: [SI-LIST] : Decoupling caps and power plane effects
Author: Non-HP-todd.l.bermensolo ([email protected]) at
HP-ColSprings,mimegw1
Date: 5/17/99 11:55 AM
To calculate the required number of decoupling capacitance for a given
motherboard, I am trying to setup lumped RLC circuit to model the behavior
of a realistic capacitor discharging into a power plane. The modeling of
the realistic capacitor just involved RLC elements all in series. The ESR
is determined from the vendors datasheet. The ESL from the datasheet as
well as the loop inductance when placed on the PCB. To model the presence
of the power plane is proving more involved.
When a chip on a circuit board has its initial current draw from its outputs
switching, the power plane is the first to respond with current. This is
due to the low inductance of the power plane. Next the ceramic capacitors
respond, followed by the higher ESL caps and then finally the power supply.
The effect of the power plane responding to the IC's current draw is the
topic which I would appreciate assistance on. At time t=0, an IC chip's
outputs switch and its power pins will draw a current Io from the power
plane of a motherboard. Since the power plane is essentially a large
capacitor, its discharging current will decrease the voltage level of the
plane until the ceramics respond to stabilize...then the bulks...then the
power supply. The rate at which the power plane discharges is of interest
to me. If the effective capacitance of the power plane seen by a chip can
be gauged, then the discharge rate of the power plane supplying current to
some load can be modeled with a lumped capacitave element. With the
discharge of the power supply predictable, then decoupling capacitance can
be calculated to prevent the power plane voltage from drooping below a
specified voltage.
Has anyone done any power/ground studies that would shed light on this
problem? Are any of my assumptions invalid?
Thanks all.
Todd Bermensolo
Intel Corp
High End Server Division
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