RE: [SI-LIST] : Stackup Extraction

apanella ([email protected])
Fri, 27 Aug 1999 10:27:40 -0700

For what it is worth...
I always try to keep the pcb house to hold one tolerance and
adjust/craft/other the other transmission line parameters as required to
meet a given impedance. In hindsight, I guess this is two things that I
a) impedance
b) one of the transmission line geometries (i.e. signal to ground
height OR
trace width OR space width OR other.. notice that these are not "AND's")

For some reason, this seems to be a good compromise between pcb house
capabilities and final design requirements...

Oh but wait.... which geometry should be specified...??? I believe
the specified geometry depends on the application. For instance... if
are creating a pcb that will be used as an edge card... it may be best
specify the height between the outer signal to ground height...

I know this isn't perfect... but rather a comprimise... However, as we
know many options will work... but some are more important than others
for a
given application.

Just another reference point...

Best Regards,
[email protected]

> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Abe Riazi
> Sent: Monday, August 16, 1999 12:43 PM
> To: '[email protected]'
> Subject: RE: [SI-LIST] : Stackup Extraction
> Patrick:
> Thanks for your response.
> I always pay a close attention to effects of manufacturing tolerance
> variations. SI simulations are carried out for three corners (i.e.
> fast, typ and slow), and numerous model and PCB parameters are allowed
> to vary according to tolerance requirements. For instance, the value of
> substrate dielectric constant may be 4.2 for fast, 4.4 for typical and
> 4.6 for slow corners. Similarly, substrate thickness for fast, typical
> and slow corners can be 5.2 mils, 4.5 mils, and 3.8 mils respectively.
> This is considered necessary to verify the design under all conditions.
> Experience has proven to me that "stackup extraction", which I had
> attempted to explain clearly in my communication, is important. It can
> serve to eliminate numerous SI simulation problems and enhance
> simulation accuracy.
> Best Regards,
> Abe
> >----------
> >From: Patrick Riffault[SMTP:[email protected]]
> >Sent: Monday, August 16, 1999 4:46 AM
> >To: [email protected]; '[email protected]'
> >Cc: Ken Hempen; Walt Otto
> >Subject: Re: [SI-LIST] : Stackup Extraction
> >
> >At 08:10 AM 8/15/99 -0700, Abe Riazi wrote:
> >
> >Abe
> >
> >Although obtaining an accurate representation of a stackup is
> >necessary when doing simulations I would not rely on the
> >extracted information to determine if a board passes SI.
> >
> >I would use the ranges that were specified when the PCB
> >was designed to ensure that everything will work over all manufacturing
> >ranges (example dielectric of 4.1 to 4.7, trace width of
> >4.8 to 5.2 mils). The extracted information is only one of many
> >combinations permitted by the design.
> ><SNIPPED to save BW>

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