Re: [SI-LIST] : RE: Another decoupling question

Mike Degerstrom ([email protected])
Mon, 20 Sep 1999 15:52:13 -0500

On Sep 20, 10:39am, D. C. Sessions wrote:
> Subject: Re: [SI-LIST] : RE: Another decoupling question
> "Volk, Andrew M" wrote:
> >
> > "D.C. Sessions" wrote:
> >
> > >On-chip decoupling isn't so much expensive in die area (because die
> > >area is generally interconnect-dominated) but it does impact on yield
> > >because of the increase in gate-oxide area where a gate failure can
> > >cause a supply short.
> >
> > Oh, I disagree. If the chip is at all I/O pad limited, inclusion of power
> > decoupling in the I/O ring is very expensive in die area. Core capacitance
> > may not be available to the I/O if they run at different voltages.
> > Capacitance located in the core area is not available to the I/O ring,
> > because of the interconnect densities you mentioned or is much less
> > effective due to the longer interconnect.
>
> Ah! I agree that providing I/O bypass capacitance on-chip is hideously
> expensive, due in equal part to the huge amount of charge storage needed
> and to the limited benefit it provides (essentially it allows the use of
> both supply and ground wires to supply SSO transients instead of just one
> or the other.)

D.C.,

Sometimes we have just one low inductance supply (usually ground) and if
we had enough capacitance on-chip then we can still run high data
rates with a poor power return for outputs that are CMOS that use
both pull-up and pull-down such as CMOS full-swing and LVTTL. So
in some cases it is a 'limited benefit' but in others it is not.

>
> IMHO the best bet for minimizing SSO transients is to use balanced codes
> such as 8b/10b so that there isn't any substantial common-mode current.
> Actually saves pins and cuts jitter too.

Not sure where you are coming from here. 8b/10b will work if you
have a DC block in your system. But for SSO transients you've got
to get current supplied during the switching event - not just average
out the current demand over 10 bits.

Can the confusion be that you have a single rail output driver, such
as GTL, in mind whereas many of us are thinking more of a two-rail
output driver such as LVTTL or full-swing CMOS?

Mike

>
> > -----Original Message-----
> > From: D. C. Sessions [mailto:[email protected]]
> > Sent: Monday, September 20, 1999 9:08 AM
> > To: [email protected]
> > Subject: Re: [SI-LIST] : RE: Another decoupling question
> >
> > "Volk, Andrew M" wrote:
> > >
> > > Chris -
> > >
> > > I agree the best capacitance is on-die. It is expensive in die area, but
> > > becoming more and more essential as edge rates and speeds increase.
> > > However, there exist devices already without such provisions and I was
> > still
> > > wondering whether capacitors can be placed under BGA packages to help
> > > existing power decoupling problems. Is it cost effective and
> > > manufacturable?
> >
> > > -----Original Message-----
> > > From: Chris Cheng [mailto:[email protected]]
> > > Sent: Friday, September 17, 1999 1:52 PM
> > > To: [email protected]
> > > Subject: RE: [SI-LIST] : RE: Another decoupling question
> > >
> > > for ~10nf, you are better of putting it insider the die. (yes, on
> > > die decouping)
> > > chris
>
> --
> D. C. Sessions
> [email protected]
>
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>
>-- End of excerpt from D. C. Sessions

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