Re: [SI-LIST] : Decoupling strategy in tight spaces

Chris Bobek (cbobek@cadence.com)
Wed, 15 Sep 1999 10:53:51 -0700

Hi Diane,

Part of the problem is the derating we have to do on this mil project. I am
trying to work this out with the customer right now. Obviously, if this were a
commercial project, I wouldn't be having this problem. In fact, I would probably
like to use the 0508 interdigitated style caps from AVX. Their series L is only
110pH, or so they say.

Thanks,

Chris

"Diane A. Delute" wrote:

> Hi Chris,
>
> Just a quick question, what voltage do you need your caps at?
>
> I get 16V 0.1uF caps in 0402 size. I use these regularly for decoupling. For
> the power I also use 10V case D (290x170x95 mils), tantalum 150uF caps. Most
> of my projects run at 2.7v to 5v nominal range.
>
> My last batch of 0.1uF, 0402 came from Capacitor Supply inc., 800-582-5700.
>
> Diane
>
> To: Si-list <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : Decoupling strategy in tight spaces
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> Reply-To: "si-list@silab.eng.sun.com, Chris Bobek" <cbobek@cadence.com>
>
> Hi,
>
> I am trying to come up with a decoupling strategy for a board I'm
> working on. Unfortunately, there are some constraints that make it more
> difficult than other boards I've done.
>
> For various reasons (i.e., mil project), we have the following
> capacitors to work with:
>
> 4700pF -- 0805 (largest value for smallest case size, for our
> application)
> 0.1uF -- 1812 ("")
> 15uF -- 0.6ohm ESR, 1412
>
> For parts with a lot of switching and I/O, my thoughts were to:
> - use a 4700pF at each power pin because it has a smaller case size than
> the 0.1uF which will yield lower inductance, thus better response for
> higher freq's.
> - use a 0.1uF at each power pin for most of the other freq's.
> - use the low ESR 15uF where possible to provide large switching
> currents
>
> For other, smaller parts, I would just use a mix of 4700's and 0.1's.
>
> Are there any major problems with my reasoning? Does anybody have
> "better" recommendations... and can back them up ;-)
>
> I will follow this question up with another later, concerning capacitor
> placement and vias.
>
> Thank you,
>
> Chris
>
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