Assuming switching noise spikes are symmetrical in power and ground
lines, they can be interpreted as a transient drop (or increase) in the
supply voltage of the gates connected to that noisy power supply lines.
the two complementary last stages of the differential clock generator
simultaneously with a transient drop in the power supply lines due to
switching noise, both the true signal (i.e. raising) and the
clock signal (falling) will be slowed down. This means that the
clock signal has an overall delay increase, compared with the case when
transient drop occurs simultaneously with the clock signal switching at
differential drivers. Thus, the switching noise induces clock jitter
differential clock signaling is used.
Has anybody experienced this or measured the effect of simultaneous
noise on differential clock jitter?
Jose Luis Gonzalez
-- Now at: Electrical and Computer Engineering Department University of Arizona, Tucson AZ 85721, USA Phone: Office (520) 621 6023 Lab (520) 626 7078 Fax: (520) 621 8076 E-mail: email@example.com
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