[SI-LIST] : Differential clock jitter and switching noise

Luis Gonzalez (jlg@ece.arizona.edu)
Thu, 01 Apr 1999 10:24:01 -0800

I have a question about the effects of on-chip originated switching
noise in
clock jitter when using on-chip differential clock distribution.

Assuming switching noise spikes are symmetrical in power and ground
on-chip
lines, they can be interpreted as a transient drop (or increase) in the
power
supply voltage of the gates connected to that noisy power supply lines.
If
the two complementary last stages of the differential clock generator
switch
simultaneously with a transient drop in the power supply lines due to
switching noise, both the true signal (i.e. raising) and the
complementary
clock signal (falling) will be slowed down. This means that the
differential
clock signal has an overall delay increase, compared with the case when
no
transient drop occurs simultaneously with the clock signal switching at
the
differential drivers. Thus, the switching noise induces clock jitter
even if
differential clock signaling is used.

Has anybody experienced this or measured the effect of simultaneous
switching
noise on differential clock jitter?

Thank You,

Jose Luis Gonzalez

-- 
Now at: 
Electrical and Computer Engineering Department
University of Arizona, Tucson AZ 85721, USA
Phone: Office (520) 621 6023
       Lab    (520) 626 7078
Fax:          (520) 621 8076
E-mail: jlg@ece.arizona.edu

Permanent address

____________________________________________________________________________ | OOO Dep. d'Enginyeria Electronica | C/. Gran Capita s/n Modul C4 | | OOO Univ. Politecnica de Catalunya | 08034 Barcelona (Spain) | | OOO | Tel. +34 93 4016748 | | UPC | Fax +34 93 4016756 | | | E-mail: jlgonzalez@eel.upc.es|

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