Re: [SI-LIST] : Some Semiconductors are Unnecessarily Fast

Roy Leventhal (Roy_Leventhal@mw.3com.com)
Tue, 13 Jul 1999 09:41:02 -0500

Mike,

All your points are well made. More to the point of my example: We have been
dealing with edge rates of 500ps on 4MHz busses (that's right, 4.0 MHz) and
several similar cases! This makes no sense at all.

The edge rate needs to be no faster than necessary to satisfy the criteria you
mention for the fastest speed of intended application of the part in question.
Anything much faster is epensive to deal with.

Over time, the winning semiconductor companies will include such considerations
in how they design for their marketplace.

Best Regards,

Roy

"Mike Degerstrom" <degerstrom.michael@mayo.edu> on 07/12/99 04:44:09 PM

Please respond to si-list@silab.eng.sun.com

Sent by: "Mike Degerstrom" <degerstrom.michael@mayo.edu>

To: si-list@silab.eng.sun.com
cc: (Roy Leventhal/MW/US/3Com)
Subject: Re: [SI-LIST] : Some Semiconductors are Unnecessarily Fast

Roy,

You make a good point. In theory, one could "get by"
with edge rates that are one-half the cycle time and this would
allow one to utilize the cheapest packaging. However theory is
often not that close to reality due to other factors. These include
clock skew, setup and hold time uncertainty, coupled noises,
package and interconnect delays, and mismatches between switching
thresholds. With all of these factors increasing the timing
uncertainty, one would want a faster edge rate to decrease
latency and to desensitize switch points due to threshold
mismatches.

One more example is one that we just faced. It turns out that we
were trying to slow down the edge rate into a full-swing buffer. Now
with CMOS, there is some gain from your pre-drive stage to the last
stage. So we have to delay the pre-drive stage edge rate much
more than the final stage edge rate. So if we wanted a 1ns edge,
for example, we introduce another 1-2ns latency into the predrive
stage. The more latency you have, the more you need to limit
your packaging and net topology to meet timing.

With all that said, I suspect the semiconductor companies
are in a situation where they can't please everybody. If they
slowed the edges down, then some users would complain about the
additional latency. However, it certainly seems that, for your
example, one could slow down a 500ps edge rate significantly for
100Mhz operation.

Mike

On Jul 12, 3:21pm, Roy Leventhal wrote:
> Subject: [SI-LIST] : Some Semiconductors are Unnecessarily Fast
>
>
> Several recent threads have commented that few nets on a board used to be a
> signal integrity challenge in the past and now almost all are.
>
> What we are seeing are a number of instances where the semiconductor
companies
> are producing parts with edge rates way faster than the clock and application
> calls for. Parts with 500ps rise times or less and clock periods of 100ns or
> more. SI engineers are seeing more demand for their skills what with
shrinking
> geometries and lack of (care? concern?) edge rate control on drivers.
>
> But, this is "make work" and is not the road to world class competitiveness
for
> our companies. There are enough real world signal integrity problems for us
to
> tackle without any "help" of this sort from the semiconductor manufactures.
>
>
> Roy Leventhal
>
>
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com.
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>
>-- End of excerpt from Roy Leventhal

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