On my latest design I have shrunk the antipad size around the signal and power/ground plane vias from our standard 48 mils down to 42 mils. This allowed for more ground and power plane area and eliminated the possibility of creating slots in the ground planes where there are two or more vias spaced closely. This also shrinks the length of the thermal spokes thus reducing inductance on these connections. The board is 10 layers and has two BGA parts.
This doesn't really address your question or problem directly but lets you know what other folks are doing.
Sr. Electronic Engineer
777 Beta Dr.
Mayfield Village, Ohio 44143
From: Greim, Michael [mailto:firstname.lastname@example.org]
Sent: Wednesday, October 13, 1999 3:53 PM
Subject: [SI-LIST] : Of thermal reliefs and signal integrity....
I was hoping that somebody out there might have a report
that can help me out. I know that I can find it but it also
might be useful to others facing a similar problem. Under
the guise of this is always that it has been done and we
can't build boards otherwise (technical data conspicuously
absent). I am being told that all power plane connections
even SMT devices are connected to the plane via thermal
reliefs (four spoke I suppose)
Not only is this unnecessary in that the thermal drop of the
escape etch of the SMT pad should be the same or better
than four spokes, but inductance to the power plane is
increased and the power plane is chopped up, especially
in high density BGA areas where you need it the most.
If you have a report that shows this, or think that I am off
my rocker, please post as I imagine that many folks reading
this may be in a similar situation.
The bounds of Time, Space or Mechanics should never stand
in the way of a perfectly good idea.......
The time is gone, The email's over, thought I'd
something more to say.........
Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: email@example.com
199 Riverneck Road V: 978-256-0052/x1607
Chelmsford, MA 01824-2820 F: 978-256-4778
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