Please find my questions/comment below. You bring up a lot
interesting points.
On Jul 15, 10:38am, Jan Vercammen wrote:
> Subject: [SI-LIST] : respons to semiconductor I/O edge rates
> I would like to contribute to the discussion on semiconductor edge rates.
>
> I do think that semiconductor manufacturers are "inventive' with respect
> to controlling I/O edge rates. They have good reasons for it: (1) keep
> the chip working (reduce noise) and (2) use less package pins (=less
> expensive package) to reduce cost.
>
> If you follow the published literature (e.g. IEEE trans on Solid State
devices,
> IBM Journal of R&D, HP Journal, ...) you will find several articles
> on the control of the edge rates. The problem with semiconductor
manufacturing
> is the wide variation in the saturation current Ids of the switching devices,
> whereas, e.g, resistors are controlled to a few %, the Ids can vary as much
as
> a factor of 4 (or more) between process corners.
I will have to look through the literature. Does anyone have any
good references before I start?
I have an SI background but don't know devices well. However, your
1:4 variation of Ids over process corners seems very extreme compared
with the fastest vs slowest corners of the few foundrys that we
work with. What is realistic with mainstream foundrys? How
can anyone expect to design I/O with 4x Ids variations? Even
if you use these automatic impedance control techniques using
a referenence resistor, I can't imagine that it would be
much fun trying to design the comparator circuit used in
the impedance control approaches.
>
> The on-chip switching of I/O drivers is typically in the order of 100-200ps,
or
> smaller, for VLSI devices such as the clock drivers or microprocessor chips
> (e.g. PowerPC 604, 740, ...), even with a 50R load. This is documented in
> IBIS files. However, externally observed I/O edge rates are about 2-5 times
> slower. I have studied Spice models of clock drivers and compared them to
> measuremnt. They confirm that external edges are slower and I do not think
that
> the Spice models are wrong, it is the package model that is insufficient.
I remember about 10 years ago that you could get a full package model
for National (I think) parts. Now it seems that all you get is
some silly little series inductor when you get ibis models, for example.
It stands to reason that edge-rate should vary substantially with
respect to where the ground and/or power returns are with respect
to the switching pin. We put a random pattern into all 8 inputs
of an octal buffer and loaded the outputs with about a 1ns 50 ohm
transmission line. There was variation from pin to pin. The
eye diagrams for each pin showed a lot of variation due to differing
switching patterns (our transmission line loads were not coupled
and so we can rule out crosstalk). Worst of all, the falling
edge would have a very long tail even though the rising edge
would come up very cleanly. This was interesting since the power
and ground pin ratio and placement was quite symmetrical. I can
only suppose that the output buffer design was much more sensitive
to power droop than to ground rise.
>
> There are several reasons why the external observed edge rate of I/O drivers
> is smaller: they are due to the package and, very likely, due to the internal
> on-chip power distribution (cfr e.g. IBM article in IEEE trans CPMT).
>
> - the power supply bounce in the vcc and gnd, due to the finite impedance
> of the package causes the I-V curves of the output drivers to shift such
that
> they tend to deliver less drive current. This "negative feedback" effect
> is well documneted in the literature.
> - the package contains, inevitably, some additional attenuation due to skin
> effect losses. The material of the package is very important in this
respect,
> e.g. some packages use alloy-42 (or a similar material) which is not as
good a
> conductor as e.g. palladium-copper leadframes (alloy-42 has additionaly
inductive
> and magnetic losses, which manifest themselves, luckily, only for relative
> low frequencies). The effect of the package material and the package pin
> geometry (e.g. thin conductors in ceramic or thin film packages) on the
very
> fast edges is significant (cfr IBM Journal of R&D on PGA packages).
>
> Several articles have been published on comparisons between alloy-42 and
> palladium-cu leadframes. The conclusion was that palladium-cu allows for
> faster edge rates, less ground bounce and less damping of ringing in
waveforms,
> whereas alloy-42 leadframes showed lower external edge rates, more ground
bounce but
> more damping of ringing.
I would have suspected that the negative-feed back effect was much
more dominant at slowing down edge rates. I guess I should research
your mention of losses in the leadframes as well.
> regards,
>
> jan vercammen
> [email protected]
>
Thanks for your information,
Mike
-- _______________________________________________________________ Mike Degerstrom Email: [email protected] Mayo Clinic 200 1st Street SW Gugg. Bldg. RM 1042A Phone: (507) 284-3292 Rochester, MN 55905 FAX: (507) 284-9171 WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html _______________________________________________________________**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****