The SI problems at the chip level can be very challenging due to the
very high edge rates on chip and the high signal counts.
Chip level power distribution has signal integrity problems of its own.
For instance a high performance CMOS microprocessor (Hot Chips '97) may have:
VDD = 1.8V
Pd = 70W
Clock rate = 600 MHz, period = 1667 pS
So I(average) = 70/1.8 or about 40 A
At the beginning and the end of the clock cycle the current is close to zero,
so for a simple triangle wave approximation the peak current is about 80 A.
The current on the chip has to go from nearly zero to 80 A in 833 pS,
with dI/dT around 100 GA/S.
All the while the individual fets must stay within about 10% of 1.8V
That is a serious challenge to signal integrity!
For on chip signal integrity, clock and power distribution
there are several papers available on the Simplex web site:
Here is their statement on chip level signal integrity:
Below 0.35 micron, coupling capacitance noise
and timing are a concern at the chip level.
Critical signals are no longer limited to
pre-identified "critical nets". However, it's
impractical to perform detailed signal integrity
analysis on every net of a design when you have
hundreds of thousands of nets. Simplex Solutions
has an intelligent filtering mechanism they call
SIFT that applies signal integrity criteria such
as coupling capacitance, drive strength and load
to all nets and returns a filtered list of
"signal integrity critical nets". You can
use this filtered list to drive further detailed
signal integrity analysis.
My vote is that on chip problems can be severe!
Sandy Taylor (contractor)
Phone: Orcas Island (360) 376 3815
Sunnyvale (408) 617 6175
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