I do think that semiconductor manufacturers are "inventive' with respect
to controlling I/O edge rates. They have good reasons for it: (1) keep
the chip working (reduce noise) and (2) use less package pins (=less
expensive package) to reduce cost.
If you follow the published literature (e.g. IEEE trans on Solid State devices,
IBM Journal of R&D, HP Journal, ...) you will find several articles
on the control of the edge rates. The problem with semiconductor manufacturing
is the wide variation in the saturation current Ids of the switching devices,
whereas, e.g, resistors are controlled to a few %, the Ids can vary as much as
a factor of 4 (or more) between process corners.
The on-chip switching of I/O drivers is typically in the order of 100-200ps, or
smaller, for VLSI devices such as the clock drivers or microprocessor chips
(e.g. PowerPC 604, 740, ...), even with a 50R load. This is documented in
IBIS files. However, externally observed I/O edge rates are about 2-5 times
slower. I have studied Spice models of clock drivers and compared them to
measuremnt. They confirm that external edges are slower and I do not think that
the Spice models are wrong, it is the package model that is insufficient.
There are several reasons why the external observed edge rate of I/O drivers
is smaller: they are due to the package and, very likely, due to the internal
on-chip power distribution (cfr e.g. IBM article in IEEE trans CPMT).
- the power supply bounce in the vcc and gnd, due to the finite impedance
of the package causes the I-V curves of the output drivers to shift such that
they tend to deliver less drive current. This "negative feedback" effect
is well documneted in the literature.
- the package contains, inevitably, some additional attenuation due to skin
effect losses. The material of the package is very important in this respect,
e.g. some packages use alloy-42 (or a similar material) which is not as good a
conductor as e.g. palladium-copper leadframes (alloy-42 has additionaly inductive
and magnetic losses, which manifest themselves, luckily, only for relative
low frequencies). The effect of the package material and the package pin
geometry (e.g. thin conductors in ceramic or thin film packages) on the very
fast edges is significant (cfr IBM Journal of R&D on PGA packages).
Several articles have been published on comparisons between alloy-42 and
palladium-cu leadframes. The conclusion was that palladium-cu allows for
faster edge rates, less ground bounce and less damping of ringing in waveforms,
whereas alloy-42 leadframes showed lower external edge rates, more ground bounce but
more damping of ringing.
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****