Not for long.
> Doesn't the trigger voltage (threshold) voltage scale
> proportionally to the VDD applied? I'm curious because I really want
> to operate some LVC parts at this voltage and can't get a good answer
> from the semiconductor help line (TI) that explains why or why not this
> would work. Is the output transistor pair setup identically to 5V CMOS
The final drive pair _per_se_ is almost certainly the same. The devices
themselves are the issue.
The molecules in current-generation gate oxide thicknesses can be counted
on your hands. The fields even at 3v are near the breakdown stresses
for silica; stray thermal carriers can be trapped in the oxide, the
oxide/silicon interface, and lattice discontinuities near the surface.
Carriers in the short device channels are nearly ballistic and approach
the energies needed to knock atoms out of lattice alignment. (And
there's lots more.)
In short, a modern CMOS transistor is a very violent place, and the
violence scales quite nonlinearly with voltage. VLSI insists on
design rules that ensure a 10-year lifetime with minimal parametric
degradation under worst-case conditions, and that means holding
the supply voltage for our 1.8v process to no more than 2.05v
> I have been doing this experimentally and see no obvious reason
> why I'd have longterm failures.
Believe me: you will. If you want to convince yourself, take a
low-voltage part and put it in a ring oscillator with fair-sized
load capacitance (say about 30pf/stage) Run it up to 5.25v and
100 degrees C and measure the frequency. Leave it that way for
a week and measure the frequency again. If it's still running.
The days when you could abuse CMOS with impunity are long gone.
-- D. C. Sessions email@example.com
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