How about this:
IDS=IDsat(1-VDS/VT)^2 for VDS => VT
This is more of a "JFET-style" equation but the above equation
seems to lend itself to analysis better than what Gray/Meyer give
in their textbook for mosfets as:
where I have omitted the (1+lamba*VDS) from my equation
above to simply further analysis.
If we are satified with the top equation, then my question
still stands. How much +/- 3 sigma variation can we expect
for IDsat for a mainstream CMOS process at a fixed temperature?
I do have information from a .25u process that, when I do
the DC curves on their process corners, tells me to expect only
+/- 11% IDsat variation at 25C. This is from a big IC supplier
and they are known for their thoroughness so I assume that
the +/- 11% is a +/- 3 sigma number. However it is much
less variation than I expected. So maybe I did the simulation
On Aug 20, 3:41pm, D. C. Sessions wrote:
> Subject: Re: [SI-LIST] : Idsat variation
> Mike Degerstrom wrote:
> > Jim,
> > Thanks for your reply. I'm no device physicist but I don't
> > think Idsat should be a function of voltage.
> Of course it is. You even point it out, below.
> > Certainly voltage
> > variation affects a CMOS buffer drive strength. However
> > I was asking for Idsat for the following equation relating drain current
> > to the gate-to-source voltage for a CMOS device in the ohmic region:
> > ID=IDsat(VGS-VT)^2
> This doesn't work. The dimensions are wrong. Perhaps you meant
> which is equivalent to
> But in all cases Id depends on Vgs which is generally dependent on Vdd.
> > Also, I haven't been able to find the relationship between Idsat
> > and temperature in my text books.
> It's not simple because Vt and transconductance have opposite
> temperature responses, so the effect on Idsat depends on the
> bias point. Clever designers (this should come as no surprise)
> take advantage of this to produce low tempco current references.
> D. C. Sessions
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>-- End of excerpt from D. C. Sessions
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