I think you don't need ultra fast edge rates to be in trouble because of
overshoot and undershoot. If my humble experience can help you we once had a
terrible time understanding why a system was failing erratically knowing
that this same system had been working perfectly for 5 years. We finally
discovered that we had more overshoot and undershoot on signals in a bus
extension path. This over and undershoot occurred because of a die shrink on
one of the component at the interface. Terminating the lines got rid of the
problems. We worked closely with the manufacturer of the component to try to
quantify the effect of undershoot and overshoot we never got a clear answer
to that and it is somehow understandable.
JOACHIM MUELLER wrote:
> We find that that with the sub nano second edges on today's drivers,
> almost every unterminated signal has an overshoot that exceeds the
> maximum voltage rating on the input, if it is more than 1inch away from
> the output.
> As an example, I am driving with a 500ps edge into a SAMSUNG Memory
> KM736V887. The SSRAM is 2 inch away from the driving chip, and my
> simulation result shows an overshoot of 4.2V in a point-to-point
> topology. Samsung specifies a 'absolute maximum voltage' for this input
> of 3.6V.
> Would you put a series termination on this net?
> Those maximum voltage specs, we find in the data sheets consider a DC
> voltage, but what would be the AC margin for this parameter. Of course
> it is higher - but how high? Could I consider 2 times the DC maximum
> voltage rating for transients as a safe and simple design rule?
> I guess the question is, does anybody care about overshoot on
> data/address busses before the actual sampling time? If yes, what would
> you consider to be an acceptable overshoot?
> Our products have to meet long term reliability requirements and I would
> think latch up can not be the only failure mechanism to consider.
> Any comments would be greatly appreciated
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