Two things that could go wrong when inputs linger near the actual
threshold level, are (1) false triggering or oscillation, unless inputs
have hysteresis (Schmitt triggered), and (2) excessive current through
the input gate from Vdd to Vss when both P and N channel FETs are
2ns to go from 1.5V to 0.8V (0.35V/ns) is not terribly slow. Yet what
is fine for one device may be too slow for another. It depends on the
speed and design of the chip. "CMOS" covers a huge range of speeds.
>Based on its' timing specification , the setup time measurement is to
>1.5V on a clock rising edge to 1.5V on the falling edge of the signal.
>Shall it be 1.5V on the clock rising edge to 0.8V of the falling edge
>for the setup time measurement?
>That is because 0.8Volt is a guarantied low state.
Most data sheets include the slew rate or rise/fall times at which the
chip is to be tested. And in the end that is what matters, since any
chip you buy has to pass the test criteria on a chip tester.
If your actual waveforms have the same rise/fall times as those at which
it was tested, then you could measure your timing at 1.5V for both clock
When the actual rise/fall times don't match the tester, you need to
apply some adjustments.
The conservative method is to ignore the edge rates, and treat the
entire region between Vil(max) and Vih(min) as a "no-man's land" where
you have no idea whether the chip sees it as High or Low. A rising edge
ceases to be Low when it crosses Vil(max), and doesn't become High until
it reaches Vih(min). The actual switch point is somewhere in there, we
just don't know where. To check setup time, compare the latest data
(when the falling edge last crosses Vil(max)) against the earliest clock
(when its rising edge crosses Vil(max)).
You could be even more conservative by taking your measurements a little
below Vil(max) and a little above Vih(min), to allow some "overdrive,"
or to add margin for things like noise that you might have missed.
Somewhat less conservative is to consider the tester's rise/fall times.
If the data sheet specifies a 1V/ns input edge rate (applied by the
tester), then for TTL/LVTTL signaling levels, the times measured by the
tester at 1.5V would be 0.7ns different from the time at which the
signal had crossed Vil(max), and 0.5ns different from when the signal
had crossed Vih(min). If you make all your measurements at Vil(max) and
Vih(min), you might apply these adjustment factors (in the right
direction, depending on whether the signals are rising or falling) to
the times you measure.
For example, if your falling data edge reaches Vil(max) at time t1, and
your rising clock reaches Vil(max) at time t2, you could use (t1-0.7ns)
and (t2+0.7ns) in your setup time check.
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