Re: [SI-LIST] : Thin Power Plane Dielectrics

Ray Anderson (raymonda@radium.eng.sun.com)
Wed, 20 Oct 1999 10:27:10 -0700 (PDT)

ctwardy@nortelnetworks.com comments:

>
> Does this mean ,for a given PCB size, I can increase the number of "points of consumption"
> by a factor of 10 and maintain the same capacitance per "point of consumption"?
>
Yeah, I think so, if I understand your question... If you increase
the number of "points of consumption" by 10X i.e. put 10X the number
of chips on the board and they are spaced appropriately such that each chip
draws current from its own little disk of PCB real estate then you probably
can have the same # of Farads/chip as you would have on a lower C board
with fewer chips. Not sure if that is what you were getting at.

> >
> >
> > Therefore even though the capacitance per unit area has increased
> > 10X, the available capacitance to supply current within a specified
> > time hasn't increased a bit. At lower frequencies the slowing of the
> > time of flight isn't an issue, but then again we usually aren't depending
> > on the charge storage capailities of the planes at those frequencies anyway.
>
> Will this lower the resonant frequency of the PCB power planes?
>

Yes it will. This can also introduce problems in that you will
end up having the board resonate at lower frequencies that it would have with lower Er
dielectrics. This can cause EMI concerns at lower frequencies
than you might traditonally expect. Also, the board resonance effects
will begin to move down towards the frequencies that one usually thinks
of as being primarily of SI concern. This can cause all manner of interesting
effects.
> >
>

>
> Typically interplane spacing is 5 or 10 mil.
> Reducing this by 1/10 is not a real option.

Actually it is an option today with some vendors offering alternate
technologies in lieu of thin FR4. Half mil (or less) is in the realm
of doability.

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