> Now I have a ASIC package design.There is a lot of data bus and a clock signal in this package.
> How can I do the pin assigns?If I put the clock pin beside the data pins and insert a gnd pin,can it improve the SI?
> I need your helps and wish can get some advices about how to pin assign the ASIC package.I know it is very key in HSSD to pin assign the connector and I can get a good pin assign by simulation.
There are a couple of ways that bus noise can get into your clock lines.
Obviously, sharing power and ground between the drivers and the clock receiver
(classical ground bounce) is one of the worst, although in a fully synchronous
environment it's not as bad as it might seem since the outputs are generally
quietest when the clock switches. Just don't use a PLL or DLL to advance the
output transitions to be coincident with the clock edge.
Once you give the clock reasonably quiet reference busses, the next gotcha
most people think about is capacitive coupling. In pursuit of capacitive
shielding they tend to guard the clock line with power and ground lines.
IF these are quiet power and ground (or in selected cases core power/ground
pairs, with caveats) then all well and good.
The big nasty is that all too often the power and ground are I/O power and
ground (after all, they're the ones we need the most, and we have plenty to
assign to the job.) BAD idea -- REALLY bad idea. Unlike core power and
ground, I/O power and ground are inherently unbalanced. What's more, each
I/O supply line carries the switching current from several signal lines,
and it turns out that inductive coupling within the package is very strong
within the package, far more so than the capacitive coupling. So those
supply lines are arguably the WORST lines you could put next to your clock.
As others have said, your best bet is a differential clock. If you can't
get a differential clock source, at least use a differential receiver with
an external reference voltage so that your noise sources couple into them
both more or less equally.
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