RE: [SI-LIST] : Automatic/Semi-automatic design check of PCB layo

Harris, George (George.Harris@compaq.com)
Thu, 02 Sep 1999 14:31:06 -0700

Ron,

There is indeed such a product. Contact Hyperlynx at hyperlynx.com

-George
George Harris
Tel: 508-467-8893
george.harris@compaq.com
COMPAQ Computer Corporation

-----Original Message-----
From: Ron Miller [mailto:rmiller@Brocade.COM]
Sent: Thursday, September 02, 1999 1:18 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Automatic/Semi-automatic design check of PCB layout
database for crosstalk/SI violations.

Hi Guys

What technique or tools are being used for checking a new PCB layout
database for simple
mistakes, like excess crosstalk or "BIG" impedance mismatches before
releasing a PCB
for FAB.

My focus is the housekeeping signals and lower speed busses, that we
usually
neglect but which
can still bite us in the posterior, causing a new spin of artwork and
FAB.

Requirements in order of importance:
1. Compatibility with PCB databases like Allegro/Cadence
2. Simple to use, little or no training
3. Cost of acquiring
4. Speed of processing

If there is not such a product someone needs to get busy.

Ron Miller

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