Re: [SI-LIST] : HSTL voltage levels

Dan Bostan (dan@uniant.com)
Mon, 2 Aug 1999 11:05:49 -0500

I am also very much interested in this topic.
Thank you.

Dan Bostan
Engineer
Corvia Networks e-mail: dan@corvia.com
212 Gibraltar Dr. ph: 408.752.0550/x111
Sunnyvale, CA 94089 fax: 408.752.0551

----- Original Message -----
From: fabrizio zanella <fzanella@fishbowl02.lss.emc.com>
To: <si-list@silab.eng.sun.com>
Sent: Friday, July 30, 1999 8:14 AM
Subject: [SI-LIST] : HSTL voltage levels

> Hello,
> can someone share experiences with using HSTL as an I/O buffer for driving
> point to point at 100MHz and faster? What confuses me are the Vref and
Vtt
> values specified in the HSTL Jedec spec and in data sheets from
> manufacturers - Vref=0.9v, Vtt=1.5v. I have performed some measurements
> and simulations with the specified Vref level of 0.9V and it does not make
> sense, the signal swings I see are from 0.7 to 2.5V, therefore there is no
> margin at the low side. Is it possible to change Vref to 1.5V, like with
> SSTL and GTLP technologies?
>
> thanks very much,
>
> Fabrizio Zanella
> EMC, Hardware Engineering
> fzanella@emc.com
> 508-435-2075, x4645
>
>
> **** To unsubscribe from si-list: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP. si-list archives are accessible at
http://www.qsl.net/wb6tpu/si-list ****
>
>

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****